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PDF AT93C66B Data sheet ( Hoja de datos )
| Número de pieza | AT93C66B | |
| Descripción | (AT93C56B / AT93C66B) Three-wire Serial Electrically Erasable Programmable Read-only Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Low-voltage and standard-voltage operation
– VCC = 1.7V to 5.5V
• User-selectable internal organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire serial interface
• Sequential read operation
• 2MHz clock rate (5V)
• Self-timed write cycle (5ms max)
• High reliability
– Endurance: One million write cycles
– Data retention: 100 years
• 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN, 8-lead XDFN, and 8-ball VFBGA
packages
Description
The Atmel® AT93C56B/66B provides 2048/4096 bits of serial electrically erasable pro-
grammable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
(when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the
ORG pin is tied to ground). The device is optimized for use in many industrial and commer-
cial applications where low-power and low-voltage operations are essential. The
AT93C56B/66B is available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
UDFN, 8-lead XDFN, and 8-ball VFBGA packages.
The AT93C56B/66B is enabled through the chip select pin (CS) and accessed via a
three-wire serial interface consisting of data input (DI), data output (DO), and shift clock
(SK). Upon receiving a read instruction at DI, the address is decoded and the data is clocked
out serially on the data output pin, DO. The write cycle is completely self-timed, and no sep-
arate erase cycle is required before write. The write cycle is only enabled when the part is in
the erase/write enable state. When CS is brought high following the initiation of a write
cycle, the DO pin outputs the ready/busy status of the part.
The AT93C56B/66B operates from 1.7V to 5.5V.
8-lead SOIC
8-lead TSSOP
Figure 0-1. Pin Configurations
Pin Name
CS
Function
Chip Select
CS 1
SK 2
DI 3
DO 4
CS 1
8 VCC
SK 2
7 NC
DI 3
6 ORG
DO 4
5 GND
8 VCC
7 NC
6 ORG
5 GND
SK Serial Data Clock
8-lead UDFN
8-lead XDFN
DI
DO
GND
VCC
ORG
NC
Serial Data Input
Serial Data Output
Ground
Power Supply
Internal Organization
No Connect
VCC 8
NC 7
ORG 6
GND 5
1 CS
2 SK
3 DI
4 DO
VCC 8
NC 7
ORG 6
GND 5
1 CS
2 SK
3 DI
4 DO
Bottom view
8-ball VFBGA
Bottom view
VCC
NC
ORG
GND
8
7
6
5
1 CS
2 SK
3 DI
4 DO
Bottom view
Three-wire
Serial Electrically
Erasable
Programmable
Read-only Memory
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
Atmel AT93C56B
Atmel AT93C66B
8735A–SEEPR–1/11
Free Datasheet http://www.datasheet4u.com/
1 page  
Atmel AT93C56B/66B
Table 1-4. Instruction Set for the Atmel AT93C56B and Atmel AT93C66B
Op
Instruction SB Code
Address
x 8 x 16
Data
x 8 x 16
Comments
READ
EWEN
1 10
A8 – A0
A7 – A0
1 00 11XXXXXXX 11XXXXXX
Reads data stored in memory at specified address
Write enable must precede all programming modes
ERASE
WRITE
ERAL
WRAL
EWDS
1 11
1 01
A8 – A0
A8 – A0
A7 – A0
A7 – A0
D7 – D0
1 00 10XXXXXXX 10XXXXXX
1 00 01XXXXXXX 01XXXXXX D7 – D0
1 00 00XXXXXXX 00XXXXXX
D15 – D0
D15 – D0
Erases memory location An – A0
Writes memory location An – A0
Erases all memory locations. Valid only at
VCC = 4.5V to 5.5V
Writes all memory locations. Valid only at
VCC = 5.0V ±10% and disable register cleared
Disables all programming instructions
Note: The Xs in the address field represent “don’t care” values, and must be clocked
2. Functional Description
The Atmel® AT93C56B/66B is accessed via a simple and versatile three-wire serial communication interface. Device
operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of
CS, and consists of a start bit (logic one) followed by the appropriate op code and the desired memory address location.
READ (READ): The read (READ) instruction contains the address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the serial output pin, DO.
Output data changes are synchronized with the rising edges ofthe serial clock, SK. It should be noted that a dummy bit
(logic zero) precedes the 8- or 16-bit data output string. The AT93C56B/66B supports sequential read operations. The
device will automatically increment the internal address pointer and clock out the next memory location as long as chip
select (CS) is held high. In this case, the dummy bit (logic zero) will not be clocked out between memory locations, thus
allowing for a continuous stream of data to be read.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the erase/write disable
(EWDS) state when power is first applied. An erase/write enable (EWEN) instruction must be executed first before any
programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until
an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The erase (ERASE) instruction programs all bits in the specified memory location to the logical-one
state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
ready/busy status of the part if CS is brought high after being kept low for a minimum of 250ns (tCS). A logic one at pin DO
indicates that the selected memory location has been erased and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8- or 16-bits of data to be written into the specified memory
location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO
pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250ns (tCS). A
logic zero at DO indicates that programming is still in progress. A logic one indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction and the part is ready for further
instructions. A ready/busy status cannot be obtained if CS is brought high after the end of the self-timed programming
cycle, tWP.
ERASE ALL (ERAL): The erase all (ERAL) instruction programs every bit in the memory array to the logic one state, and
is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought high after being
kept low for a minimum of 250ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%.
8735A–SEEPR–1/11
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
5. Part Markings
5.1 Atmel AT93C56B
Atmel AT93C56B/66B
8 lead SOIC
3 Rows of 8 Characters
ATMLHYWW
56BM @
AAAAAAAA
8 lead TSSOP
3 Rows
2 of 6 and 1 of 7 Characters
ATHYWW
56BM @
AAAAAAA
8 lead XDFN - 1.8x2.2mm
2 Rows of 3 Characters
8-ball VFBGA - 2.35x3.73mm 8 lead UDFN -2.0x3.0mm
2 Rows
1 of 4 and 1 of 5 Characters
3 Rows of 3 Characters
56BU
@YMXX
56B
HM@
YXX
56B
YXX
PIN 1
PIN 1
PIN 1
Catalog Number: AT93C56B
Catalog Truncation: 56B
Date Codes
Y = Year
0: 2010
1: 2011
2: 2012
3: 2013
4: 2014
5: 2015
6: 2016
7: 2017
M = Month
A: January
B: February
“ ”“
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
” “”
52: Week 52
Voltages
Blank: 2.7v min
D: 2.5v min
L: 1.8v min
M: 1.7v min
P: 1.5v min
Trace Code
XX = Trace Code (ATMEL Lot Numbers to Correspond to Code)
(e.g. XX: AA, AB...YZ, ZZ)
Lot Number
AAAAAAA = ATMEL Wafer Lot Number
Country of Assembly
@ = Country of Assembly
B = PHILIPPINES W = THAILAND
Q = MALAYSIA
H,Y = CHINA
Grade/Lead Finish Material
U: Industrial/Matt Tin
H: Industrial/NiPdAu
ATMEL Truncation
AT: ATMEL
ATM: ATMEL
ATML: ATMEL
Package Mark Contact:
TITLE
93C56BSM, AT93C56B Standard Marking Information
for Package Offering
1/12/11
DRAWING NO. REV.
93C56BSM
A
8735A–SEEPR–1/11
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AT93C66B.PDF ] | |
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