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PDF TM043NBH02 Data sheet ( Hoja de datos )
| Número de pieza | TM043NBH02 | |
| Descripción | Display Module | |
| Fabricantes | TIANMA | |
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SHANGHAI TIANMA MICRO-ELECTRONICS
TM043NBH02 V1.2
MODEL NO. :
ISSUED DATE:
VERSION :
TM043NBH02
2010-9-30
Ver 1.2
■Preliminary Specification
□Final Product Specification
Customer :
Approved by
Notes
SHANGHAI TIANMA Confirmed :
Prepared by
Checked by
Approved by
This technical specification is subjected to change without notice
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 1 of 21
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1 page  
SHANGHAI TIANMA MICRO-ELECTRONICS
TM043NBH02 V1.2
2 Input/Output Terminals
2.1 TFT LCD Panel
No Symbol
1 VLED-
2 VLED+
3 GND
4 VDD
5 R0
6 R1
7 R2
8 R3
9 R4
10 R5
11 R6
12 R7
13 G0
14 G1
15 G2
16 G3
17 G4
18 G5
19 G6
20 G7
21 B0
22 B1
23 B2
24 B3
25 B4
26 B5
27 B6
28 B7
29 GND
30 DCLK
31 DISP
32 HSYNC
I/O Description
Comment
P Back light cathode
P Back light anode
P Ground
P Power supply
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
I Data input
P Ground
I
Clock for input data. Data latched at rising edge
of this signal.
Standby mode.
I DISP =“1”: Normally operation.
DISP =“0”: Standby mode.
I
Horizontal sync input with negative polarity. If
unused, please pull high level.
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 5 of 21
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SHANGHAI TIANMA MICRO-ELECTRONICS
5.2 Input Setup Timing Parameter Setting
Parameter
Symb
ol
Min
Typ
Max
DCLK Cycle Time
Tpw 66.7
-
-
DCLK Pulse High Width
Tpwh
26.7
-
-
DCLK Pulse Low Width
Tpwl 26.7
-
-
DE Setup Time
Tdes
10
-
-
DE Hold Time
Tdeh
10
-
-
HSYNC Setup Time
Ths 10
-
-
HSYNC Hold Time
Thh 10
-
-
VSYNC Setup Time
Tvhs 10
-
-
VSYNC Hold Time
Tvhh
10
-
-
Data Setup Time
Tds 10
-
-
Data Hold Time
Tdh 10
-
-
DISP Setup Time
Tdiss
10
-
-
DISP Hold Time
Tdish
10
-
-
Note 1: tr=tf=2ns.tr, tf is defined 10% to 90% of signal amplitude.
Note 2: For parallel interface, maximum clock frequency is 15MHz.
TM043NBH02 V1.2
VDD=3.3V Ta=25℃
Unit Remark
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ms
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
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11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet TM043NBH02.PDF ] | |
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