AT45DB081E Datasheet PDF - adesto
| Part Number | AT45DB081E | |
| Description | SPI Serial Flash Memory | |
| Manufacturers | adesto | |
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AT45DB081E
8-Mbit DataFlash (with Extra 256-Kbits), 1.65V Minimum
SPI Serial Flash Memory
Features
PRELIMINARY DATASHEET
Single 1.65V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports RapidS™ operation
Continuous read capability through entire array
Up to 85MHz
Low-power read option up to 15MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
256 bytes per page
264 bytes per page (default)
Page size can be factory pre-configured for 256 bytes
Two fully independent SRAM data buffers (256/264 bytes)
Allows receiving data while reprogramming the main memory array
Flexible programming options
Byte/Page Program (1 to 256/264 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible erase options
Page Erase (256/264 bytes)
Block Erase (2KB)
Sector Erase (64KB)
Chip Erase (8-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Hardware and software controlled reset options
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
400nA Ultra-Deep Power-Down current (typical)
4.5μA Deep Power-Down current (typical)
25μA Standby current (typical)
11mA Active Read current (typical at 20MHz)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150" wide and 0.208" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
DS-45DB081E-028C–DFLASH–10/2013
Free Datasheet http://www.datasheet4u.com/
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3. Memory Array
To provide optimal flexibility, the AT45DB081E memory array is divided into three levels of granularity comprising of
sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details
the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at
the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page
level.
Figure 3-1. Memory Architecture Diagram
Sector Architecture
Sector 0a = 8 pages
2,048/2,112 bytes
Sector 0a
Sector 0b = 248 pages
63,488/65,472 bytes
Sector 1 = 256 pages
65,536/67,584 bytes
Sector 2 = 256 pages
65,536/67,584 bytes
Sector 14 = 256 pages
65,536/67,584 bytes
Block Architecture
Block 0
Block 1
Block 2
Block 30
Block 31
Block 32
Block 33
Block 62
Block 63
Block 64
Block 65
8 Pages
Page Architecture
Page 0
Page 1
Page 6
Page 7
Page 8
Page 9
Page 14
Page 15
Page 16
Page 17
Page 18
Sector 15 = 256 pages
65,536/67,584 bytes
Block 510
Block 511
Block = 2,048/2,112 bytes
Page 4,094
Page 4,095
Page = 256/264 bytes
AT45DB081E [PRELIMINARY DATASHEET]
DS-45DB081E-028C–DFLASH–10/2013
5
Free Datasheet http://www.datasheet4u.com/
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AT45DB081E electronic component. |
| Information | Total 69 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AT45DB081E.PDF Datasheet ] | |
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