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PDF 9250-08 Data sheet ( Hoja de datos )
| Número de pieza | 9250-08 | |
| Descripción | ICS9250-08 | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 9250-08 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS9250-08
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
• 3 - CPUs @2.5V, up to 150MHz.
• 17 - SDRAM @ 3.3V, up to 150MHz.
• 7 - PCI @3.3V
• 2 - IOAPIC @ 2.5V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 150MHz frequency support
• Support power management: CPU, PCI, stop and Power
down Mode form I2C programming.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• Uses external 14.318MHz crystal
Key Specifications:
• CPU – CPU: <175ps
• CPU – PCI: min = 1ns max = 4ns
• PCI – PCI: <250ps
• SDRAM - SDRAM: <500ps
Block Diagram
Pin Configuration
VDDREF
*FS2/REF1
*PCI_STOP/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
{I 2 C
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDLIOAPIC
55 IOAPIC0
54 IOAPIC_F
53 GND
52 CPUCLK_F
51 CPUCLK1
50 VDDLCPU
49 CPUCLK2
48 GND
47 CPU_STOP#
46 SDRAM_F
45 VDDSDR
44 SDRAM0
43 SDRAM1
42 GND
41 SDRAM2
40 SDRAM3
39 SDRAM4
38 SDRAM5
37 VDDSDR
36 SDRAM6
35 SDRAM7
34 GND
33 SDRAM12
32 SDRAM13
31 VDD48
30 24MHz/FS0*
29 48MHz/FS1*
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
PLL2
X1 XTAL
X2 OSC
÷2
STOP
FS[3:0]
MODE
CPU_STOP#
PCI_STOP#
{I 2 C
SCLK
SDATA
BUFFERIN
PLL1
Spread
Spectrum
LATCH
POR
4
Control
Logic
Config.
Reg.
STOP
PCI
CLOCK
DIVDER
STOP
STOP
48MHz
24MHz
IOAPIC_F
IOAPIC0
REF [1:0]
2
CPUCLK_F
1
CPUCLK [2:1]
2
6 PCICLK [5:0]
PCICLK_F
16 SDRAM [15:0]
SDRAM_F
Functionality
FS3 FS2 FS1 FS0
1111
1 1 10
110 1
1 10 0
10 11
10
10
100 1
10 0 0
0 111
0 110
0 10 1
0 100
00 11
00 10
000 1
0000
CPU
(MHz)
133
124
150
140
105
110
115
120
100.3
133
112
103
66.8
83.3
75
124
PCICLK (MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.67 (CPU/3)
38.33 (CPU/3)
40.00 (CPU/3)
33.43 (CPU/3)
44.33 (CPU/3)
37.33 (CPU/3)
34.33 (CPU/2)
33.40 (CPU/2)
41.65 (CPU/2)
37.5 (CPU/2)
41.33 (CPU/2)
9250-08 Rev H 10/8/99
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Free Datasheet http://www.datasheet4u.com/
1 page  
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit 2,
Bit 6:4
Bit 3
Bit 1
Bit 0
Description
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit2 Bit6 Bit5 Bit4 CPU clock
PCI
0111
0110
100.3
133
33.43 (CPU/3)
44.33 (CPU/3)
0101
0100
112 37.33 (CPU/3)
103 34.3 (CPU/3)
0011
0010
66.8 33.4 (CPU/2)
83.3 41.65(CPU/2)
0001
0000
75 37.5 (CPU/2)
124 41.33 (CPU/3)
1111
1110
133 33.25 (CPU/4)
124 31.00 (CPU/4)
1101
1100
150 37.50 (CPU/4)
140 35.00 (CPU/4)
1011
1010
105 35.00 (CPU/3)
110 36.67 (CPU/3)
1001
1000
115 38.33 (CPU/3)
120 40.00 (CPU/3)
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 6:4 (above)
0 - Normal
1 - Spread Spectrum Enabled (Center Spread)
0 - Running
1- Tristate all outputs
PWD
0
Note1
0
0
0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 2, 4, 5,
6 are default to 0000, and if bit 3 is written to a 1 to use Bits 2, 6:4, then these
should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
ICS9250-08
Third party brands and names are the property of their respective owners.
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
ICS9250-08
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
VOH2B IOH = -12.0 mA
Output Low Voltage
VOL2B IOL = 12 mA
Output High Current
IOH2B VOH = 1.7 V
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter, One Sigma
Jitter, Absolute
Jitter, Cycle-to-cycle
IOL2B
tr2B1
tf2B1
dt1B1
dt2B1
tsk2B1
tsk2B1
tj1σ2B1
tjabs2B1
tjcyc-cyc2B1
VOL = 0.7 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V; CPU < 120MHz
VT = 1.25 V; CPU >= 124MHz
VT = 1.25 V; CPU >= 100 MHz
VT = 1.25 V; CPU < 100 MHz
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
2
19
0.4
0.4
45
35
-250
TYP MAX UNITS
2.3 V
0.3 0.4 V
-35 -19 mA
26 mA
1.4 1.8 ns
1.35 1.8 ns
45 55
%
43 50
150 175
ps
170 240
35 150
99 +250 ps
210 250
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Output High Voltage
VOH1
IOH = -18 mA
Output Low Voltage
VOL1
IOL = 9.4 mA
Output High Current
IOH1 VOH = 2.0 V
Output Low Current
IOL1 VOL = 0.8 V
Rise Time1
tr1 VOL = 0.4 V, VOH = 2.4 V
Fall Time1
tf1 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle1
dt1 VT = 1.5 V
Skew1 window
tsk1 VT = 1.5 V; All PCI clocks including PCI0
tsk1 VT = 1.5 V; All PCI clocks except PCI0
Jitter, One Sigma1
tj1σ1 VT = 1.5 V
Jitter, Absolute1
tjabs1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
2.4 2.9
0.2 0.4
-52 -22
25 41
0.5 2.2 2.6
0.5 1.8 2.2
46 50 56
400 850
250 500
15 150
-250 60 250
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
Third party brands and names are the property of their respective owners.
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet 9250-08.PDF ] | |
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