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PDF UJA1164 Data sheet ( Hoja de datos )
| Número de pieza | UJA1164 | |
| Descripción | Mini high-speed CAN system basis chip | |
| Fabricantes | NXP Semiconductors | |
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UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Rev. 2 — 17 April 2014
Product data sheet
1. General description
The UJA1164 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a
microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The
UJA1164 can be operated in a very low-current Standby mode with bus wake-up
capability and supports ISO 11898-6 compliant autonomous CAN biasing.
The UJA1164 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898
including CAN FD, additional timing parameters defining loop delay symmetry are
included. This implementation enables reliable communication in the CAN FD fast phase
at data rates up to 2 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC to
be adapted for use in a specific application. This makes it possible to configure the
power-on behavior of the UJA1164 to meet the requirements of different applications.
2. Features and benefits
2.1 General
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins and on pin
BAT
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby mode with full wake-up capability
1 page  
NXP Semiconductors
6. Functional description
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
6.1 System controller
The system controller manages register configuration and controls the internal functions
of the UJA1164. Detailed device status information is collected and made available to the
microcontroller.
6.1.1 Operating modes
The system controller contains a state machine that supports six operating modes:
Normal, Standby, Reset, Forced Normal, Overtemp and Off. The state transitions are
illustrated in Figure 3.
6.1.1.1 Normal mode
Normal mode is the active operating mode. In this mode, all the hardware on the device is
available and can be activated (see Table 3). Voltage regulator V1 is enabled to supply the
microcontroller.
The CAN interface can be configured to be active and thus to support normal CAN
communication. Depending on the SPI register settings, the watchdog may be running in
Window or Timeout mode.
Normal mode can be selected from Standby mode via an SPI command (MC = 111).
6.1.1.2 Standby mode
Standby mode is the UJA1164’s power saving mode, offering reduced current
consumption. The transceiver is unable to transmit or receive data in Standby mode. The
SPI remains enabled and V1 is still active; the watchdog is active (in Timeout mode) if
enabled.
If remote CAN wake-up is enabled (CWE = 1; see Table 24), the receiver monitors bus
activity for a wake-up request. The bus pins are biased to GND (via Ri(cm)) when the bus is
inactive for t > tto(silence) and at approximately 2.5 V when there is activity on the bus
(autonomous biasing).
Pin RXD is forced LOW when any enabled wake-up event is detected. This can be either
a regular wake-up (via the CAN bus) or a diagnostic wake-up such as an overtemperature
event (see Section 6.8).
The UJA1164 switches to Standby mode via Reset mode:
• from Off mode if the battery voltage rises above the power-on detection threshold
(Vth(det)pon)
• from Overtemp mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
Standby mode can also be selected from Normal mode via an SPI command (MC = 100).
UJA1164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 53
5 Page 
NXP Semiconductors
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
register (see Table 8). Note that this register is located in the non-volatile memory area
(see Section 6.8). In Forced Normal mode (FNM), the watchdog is completely disabled. In
Software Development mode (SDM), the watchdog can be disabled or activated for test
purposes.
Information on the status of the watchdog is available from the Watchdog status register
(Table 9). This register also indicates whether Forced Normal and Software Development
modes are active.
Table 8. SBC configuration control register (address 74h)
Bit Symbol Access Value Description
7:6 reserved R
-
5:4 V1RTSUC R/W
V1 reset threshold (defined by bit V1RTC) at start-up:
00[1]
V1 undervoltage detection at 90 % of nominal value at
start-up (V1RTC = 00)
01 V1 undervoltage detection at 80 % of nominal value at
start-up (V1RTC = 01)
10 V1 undervoltage detection at 70 % of nominal value at
start-up (V1RTC = 10)
11 V1 undervoltage detection at 60 % of nominal value at
start-up (V1RTC = 11)
3 FNMC
R/W
Forced Normal mode control:
0 Forced Normal mode disabled
1[1] Forced Normal mode enabled
2 SDMC
R/W
Software Development mode control:
0[1] Software Development mode disabled
1 Software Development mode enabled
1:0 reserved R
-
[1] Factory preset value.
Table 9. Watchdog status register (address 05h)
Bit Symbol Access Value Description
7:4 reserved R
-
3 FNMS R
0 SBC is not in Forced Normal mode
1 SBC is in Forced Normal mode
2 SDMS R
0 SBC is not in Software Development mode
1 SBC is in Software Development mode
1:0 WDS
R
watchdog status:
00 watchdog is off
01 watchdog is in first half of window
10 watchdog is in second half of window
11 reserved
UJA1164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 53
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UJA1164.PDF ] | |
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