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PDF RK3188 Data sheet ( Hoja de datos )
| Número de pieza | RK3188 | |
| Descripción | Technical Reference Manual | |
| Fabricantes | Rockchip | |
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RK3188Technical Reference ManualRev 1.2
Chapter 1 Introduction
RK3188 is a low power, high performance processor for mobile phones, personal
mobile internet device and other digital multimedia applications, and integrates
quad-core Cortex-A9 with separately NEONand FPU coprocessor.
Many embedded powerful hardware engines provide optimized performance for
high-end application. RK3188 supports almost full-format video decoder by
1080p@60fps, also support H.264/MVC/VP8 encoder by 1080p@30fps,
high-quality JPEG encoder/decoder, special image preprocessor and
postprocessor.
Embedded 3D GPU makes RK3188 completely compatible with OpenGL ES2.0
and 1.1, OpenVG 1.1. Special 2D hardware engine with MMU will maximize
display performance and provide very smoothly operation.
RK3188 has high-performance external memory
interface(DDR3/LPDDR2/LVDDR3) capable of sustaining demanding memory
bandwidths, also provides a complete set of peripheral interface to support very
flexible applications as follows :
z 2 banks, 8bits/16bits Nor Flash/SRAM interface
z 4 banks, 8bits/16bits async Nand Flash,LBA Nand Flash and 8bits sync
ONFI Nand Flash, allup to 60bits hardware ECC
z Totally 2GB memory space for 2 ranks, 16bits/32bits DDR3-800,
LPDDR2-800, LVDDR3-800
z Totally 3-channels SD/MMC interface to support MMC4.41, SD3.0,
SDIO3.0 or eMMC
z Dual-channels TFT LCD interface with 4-layers , 2048x1536 maximum
display size
z One-channels, 8bits BT656 interface, 16bits BT601 DDR interface and
10bits/12bits raw data interface with image preprocessor
z Audio interface: one 2ch I2S/PCM interface and SPDIF tx interface
z One USB OTG 2.0 and one USB Host2.0 interface and HSIC interface
z 10M/100M RMII ethernet interface
z GPS interface
z High-speed ADC interface and TS stream interface
z Lots of low-speed peripheral interface : 5I2C, 4UART, 2SPI,4 PWM
This document will provide guideline on how to use RK3188 correctly and
efficiently. The chapter 1 and chapter 2 will introduce the features, block
diagram, signal descriptions and system usage of RK3188, the chapter 3
through chapter 45 will describe the full function of each module in detail.
1.1 Features
1.1.1 MicroProcessor
z Quad-core ARM Cortex-A9 MPCore processor, a high-performance,
low-power and cached application processor
z Full implementation of the ARM architecture v7-A instruction set, ARM Neon
Advanced SIMD (single instruction, multiple data) support for accelerated
media and signal processing computation
z Superscalar, variable length, out-of-order pipeline with dynamic branch
High Performance and Low-power Processor for Digital Media Application
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Free Datasheet http://www.datasheet4u.com/
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RK3188Technical Reference ManualRev 1.2
Provides reference mode and output various duty-cycle waveform
z WatchDog
32 bits watchdog counter width
Counter clock is from apb bus clock
Counter counts down from a preset value to 0 to indicate the occurrence
of a timeout
WDT can perform two types of operations when timeout occurs:
Generate a system reset
First generate an interrupt and if this is not cleared by the service
routine by the time a second timeout occurs then generate a system
reset
Programmable reset pulse length
Totally 16 defined-ranges of main timeout period
z Bus Architecture
64-bit multi-layer AXI/AHB/APB composite bus architecture
5 embedded AXI interconnect
CPU interconnect with three 64-bits AXI masters, two 64-bits AXI
slaves, one 32-bits AHB master and lots of 32-bits AHB/APB slaves
PERI interconnect with two 64-bits AXI masters, one 64-bits AXI
slave, one 32-bits AXI slave, four 32-bits AHB masters and lots of
32-bits AHB/APB slaves
Display interconnect with six 64-bits AXI masters and one 32-bits
AHB slave
GPU interconnect with one 128-bits AXI master and 64-bits AXI
slave ,they are point-to-point AXI-lite architecture
VCODEC interconnect also with one 64-bits AXI master and one
32-bits AHB slave ,they are point-to-point AXI-lite architecture
For each interconnect with AXI/AHB/APB composite bus, clocks for
AXI/AHB/APB domains are always synchronous, and different integer
ratio is supported for them.
Flexible different QoS solution to improve the utility of bus bandwidth
z Interrupt Controller
Support 3 PPI interrupt source and 76 SPI interrupt sources input from
different components inside RK3188
Support 16 software-triggered interrupts
Input interrupt level is fixed , only high-level sensitive
Two interrupt outputs (nFIQ and nIRQ) separately for each Cortex-A9,
both are low-level sensitive
Support different interrupt priority for each interrupt source, and they
are always software-programmable
z DMAC
Micro-code programming based DMA
The specific instruction set provides flexibility for programming DMA
transfers
Linked list DMA function is supported to complete scatter-gather
transfer
Support internal instruction cache
Embedded DMA manager thread
Support data transfer types with memory-to-memory,
memory-to-peripheral, peripheral-to-memory
High Performance and Low-power Processor for Digital Media Application
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Free Datasheet http://www.datasheet4u.com/
5 Page 
RK3188Technical Reference ManualRev 1.2
¾ Support 3D display
One video layer (win1)
¾ RGB888, ARGB888, RGB565, 1/2/4/8BPP
¾ Support virtual display
¾ 256 level alpha blending
¾ Support transparency color key
Hardware cursor(hwc)
¾ 2BPP
¾ Maximum resolution 64x64
¾ 3-color and transparent mode
¾ 2-color + transparency + tran_invert mode
¾ 16 level alpha blending
3 x 256 x 8 bits display LUTs
Win0 and Win1 layer overlay exchangeable
Support color space conversion:
YUV2RGB(rec601-mpeg/rec601-jpeg/rec709) and RGB2YUV
Deflicker support for interlace output
24bits to 16bits/18bitsditheringoperation
Blank and black display
Standby mode
1.1.11 Audio Interface
z I2S/PCM with 2ch
Up to 2 channels (2xTX, 2xRX)
Audio resolution from 16bits to 32bits
Sample rate up to 192KHz
Provides master and slave work mode, software configurable
Support 3 I2S formats (normal, left-justified, right-justified)
Support 4 PCM formats(early, late1, late2, late3)
I2S and PCM mode cannot be used at the same time
z SPDIF
Audio resolution: 16bits/20bits/24bits
Software configurable sample rates (48KHz, 44.1KHz, 32KHz)
Stereo voice replay with 2 channels
1.1.12 Connectivity
z SDIO interface
Compatible with SDIO 3.0 protocol
Support FIFO over-run and under-run prevention by stopping card clock
automatically
4bits data bus widths
z High-speed ADC stream interface
Support single-channel 8bits/10bits interface
DMA-based and interrupt-based operation
Support 8bits TS stream interface
Support PID filter operation
Combined with high-speed ADC interface to implement filter from
original TS data
Provide PID filter up to 64 channels PID simultaneously
Support sync-byte detection in transport packet head
Support packet lost mechanism in condition of limited bandwidth
High Performance and Low-power Processor for Digital Media Application
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Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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