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PDF UC1698U Data sheet ( Hoja de datos )
| Número de pieza | UC1698U | |
| Descripción | HIGH-VOLTAGE MIXED-SIGNAL IC | |
| Fabricantes | ULTRACHIP | |
| Logotipo |  |
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HIGH-VOLTAGE MIXED-SIGNAL IC
160 x 128RGB C-STN LCD Controller-Driver
w/ 16-bit per RGB On-Chip SRAM
Optimized for VSTN (Video-CSTN)
MP Specifications
Revision 1.21
August 7, 2008
ULTRACHIP
The Coolest LCD Drive, Ever!!
Free Datasheet http://www.datasheet4u.com/
1 page  
BLOCK DIAGRAM
POWER ON &
RESET
CONTROL
CLOCK &
TIMING
GENERATOR
CONTROL &
STATUS
REGISTER
COMMAND
HOST INTERFACE
UC1698u
160x128RGB CSTN Controller-Driver
COLUMN ADDRESS
GENERATOR
DISPLAY DATA RAM
DISPLAY DATA LATCHES
LEVEL SHIFTERS
SEG DRIVERS
VLCD & BIAS
GENERATOR
CL
CB0 CB1 Cs
Revision C1.21
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
UC1698u
160x128RGB CSTN Controller-Driver
CONTROL REGISTERS
UC1698u contains registers which control the chip operation. The following table is a summary of these
control registers, a brief description and the default values. These registers can be modified by commands,
which will be described in the next two sections, starting with a summary table, followed by a detailed
instruction-by-instruction description.
Name: The Symbolic reference of the register.
Note that, some symbol name refers to bits (flags) within another register.
Default: Numbers shown in Bold font are default values after Power-Up-Reset and System-Reset.
Name
SL
Bits
8
FLT 4
FLB 4
CA 7
RA 8
BR 2
TC 2
PM
PMO
8
7
PC 2
AC 4
Default
0H
0H
0H
0H
0H
3H
0H
40H
00H
2H
1H
Description
Scroll Line. Scroll the displayed image up by SL rows. The valid SL value is
between 0 (for no scrolling) and (159 – 2x(FLT+FLB)). Setting SL outside of
this range causes undefined effect on the displayed image.
Fixed Lines. The first FLTx2 lines and the last FLBx2 lines (relative to CEN)
of each frame are fixed and are not affected by scrolling (SL).
When FLT and/or FLB are non-zero, the screen is effectively separated into
three regions: one scrollable, surrounded by two non-scrollable regions.
When partial display mode is activated, the display of these 2xFLT and
2xFLB lines is also controlled by LC[0]. When LC[0]=1, the display will have
three sections: 2xFLT on one side non-scrollable, 2xFLB on the other side
also non-scrollable, and scrollable DST~DEN in the middle.
Display Data RAM Column Address (counted in RGB triplet)
(Used in Host to Display Data RAM access)
Display Data RAM Row Address
(Used in Host to Display Data RAM access)
Bias Ratio. The ratio between VLCD and VBIAS.
00b: 5
01b: 10
10b: 11
11b: 12
Temperature Compensation (per oC)
00b: -0.00%
01b: -0.05%
10b: -0.15%
11b: -0.25%
Electronic Potentiometer to fine tune VBIAS and VLCD
PM offset.
PMO[6]=1b: The effective PM value, PMV = PM - PMO[5:0]
PMO[6]=0b: The effective PM value, PMV = PM + PMO[5:0]
Power Control.
PC[0]: 0b: LCD 13nF
PC[1]: 0b: External VLCD
1b: 13nF < LCD 22nF
1b: Internal VLCD (10x charge pump)
Address Control.
AC[0]: WA: Automatic column/row Wraparound (Default 1 : ON)
AC[1]: Auto-Increment order
0b : Column (CA) first
1b : Row (RA) first
AC[2]: RID: RA (row address) Auto Increment Direction (L : +1 H : -1)
AC[3] : Window Program Mode
0b : Inside Mode: Write to SRAM within the window
defined by (WPC0,WPP0) and (WPC1,WPP1)
1b : Outside Mode: Write to SRAM but skip the window
defined by (WPC0,WPP0) and (WPC1,WPP1)
Revision C1.21
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UC1698U.PDF ] | |
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