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PDF Core1553BRT Data sheet ( Hoja de datos )
| Número de pieza | Core1553BRT | |
| Descripción | Handbook | |
| Fabricantes | Microsemi | |
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Core1553BRT v4.0 Handbook
Free Datasheet http://www.datasheet4u.net/
1 page  
Introduction
General Description
Core1553BRT provides a complete, dual-redundant MIL-STD-1553B remote terminal (RT), apart from
the transceivers required to interface to the bus. A typical system implementation using Core1553BRT is
shown in Figure 1 and Figure 2 on page 6.
ADC
Memory
Address
Mapper
Backend
Interface
BUSAINEN
BUSAINP
BUSAINN
BUSAOUTIN
BUSAOUTP
BUSAOUTN
Command
Legality
Checker
Command
Legality
Interface
BUSBINEN
BUSBINP
BUSBINN
BUSBOUTIN
BUSBOUTP
BUSBOUTN
Core1553BRT
RCVSTBA
RXDAINP
RXDAINN
TXINHA
TXDAINP
TXDAINN
Transceiver
RCVSTBA
RXDBINP
RXDBINN
TXINHA
TXDBINP
TXDBINN
Microsemi FPGA
Figure 1 • Typical Core1553BRT System
At a high level, Core1553BRT simply provides a set of memory-mapped subaddresses that “receive data
written to” or “transmit data read from.” The core can be configured to connect directly to synchronous or
asynchronous memory devices. Alternatively, the core can directly connect to backend devices,
removing the need for memory buffers. If memory is used, the core requires 2,048 words of memory,
which can be shared with the local CPU.
The core supports all 1553B mode codes and allows the user to designate as illegal any mode code or
any particular subaddress for both transmit and receive operations. The command legalization can be
done within the core or in an external command legality block via the command legalization interface.
Revision 3
5
Free Datasheet http://www.datasheet4u.net/
5 Page 
2 – Tool Flows
SmartDesign
Core1553BRT is available for download to the SmartDesign IP Catalog, via the Libero® System-on-Chip
(SoC)/Integrated Design Environment (IDE) web repository. For information on using SmartDesign to
instantiate, configure, connect, and generate cores, please refer to the Libero IDE/SoC online help.
The core can be configured using the configuration GUI within SmartDesign, as shown in Figure 2-1.
Figure 2-1 • Core1553BRT Configuration within SmartDesign
Revision 3
11
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