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PDF AT83251G2D Data sheet ( Hoja de datos )
| Número de pieza | AT83251G2D | |
| Descripción | 8/16-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Pin and Software Compatibility with Standard 80C51 Products and 80C51Fx/Rx/Rx+
• Plug-In Replacement of Intel’s 8xC251Sx
• C251 Core: Intel’s MCS®251 D-step Compliance
• 40-byte Register File
• Registers Accessible as Bytes, Words or Dwords
• Three-stage Instruction Pipeline
• 16-bit Internal Code Fetch
• Enriched C51 Instruction Set
• 16-bit and 32-bit ALU
• Compare and Conditional Jump Instructions
• Expanded Set of Move Instructions
• Linear Addressing
• 1 Kbyte of On-Chip RAM
• External Memory Space (Code/Data) Programmable from 64 kilobytes to 256 kilobytes
• TSC87251G2D: 32 kilobytes of On-Chip EPROM/OTPROM
– SINGLE PULSE Programming Algorithm
• TSC83251G2D: 32 kilobytes of On-Chip Masked ROM
• TSC80251G2D: ROMless Version
• Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of the Standard 80C51)
• Serial I/O Port: Full Duplex UART (80C51 Compatible) With Independent Baud Rate
Generator
• SSLC: Synchronous Serial Link Controller
• TWI Multi-master Protocol
• μWire and SPI Master and Slave Protocols
• Three 16-bit Timers/Counters (Timers 0, 1 and 2 of the Standard 80C51)
• EWC: Event and Waveform Controller
• Compatible with Intel’s Programmable Counter Array (PCA)
• Common 16-bit Timer/Counter Reference with Four Possible Clock Sources (Fosc/4,
Fosc/12, Timer 1 and External Input)
• Five Modules, Each with Four Programmable Modes:
– 16-bit Software Timer/Counter
– 16-bit Timer/Counter Capture Input and Software Pulse Measurement
– High-speed Output and 16-bit Software Pulse Width Modulation (PWM)
– 8-bit Hardware PWM Without Overhead
• 16-bit Watchdog Timer/Counter Capability
• Secure 14-bit Hardware Watchdog Timer
• Power Management
• Power-On Reset (Integrated on the Chip)
• Power-Off Flag (Cold and Warm Resets)
• Software Programmable System Clock
• Idle Mode
• Power-down Mode
• Keyboard Interrupt Interface on Port 1
• Non Maskable Interrupt Input (NMI)
• Real-Time Wait States Inputs (WAIT#/AWAIT#)
• ONCE Mode and Full Speed Real-time In-circuit Emulation Support (Third Party
Vendors)
• High Speed Versions:
– 4.5V to 5.5V
– 16 MHz and 24 MHz
• Typical Operating Current: 35 mA at 24 MHz
24 mA at 16 MHz
• Typical Power-down Current: 2 μA
• Low Voltage Version:
– 2.7V to 5.5V
– 16 MHz
8/16-bit
Microcontroller
with Serial
Communication
Interfaces
TSC80251G2D
TSC83251G2D
TSC87251G2D
AT80251G2D
AT83251G2D
AT87251G2D
Rev. 4135F–8051–11/06
1
Free Datasheet http://www.datasheet4u.net/
1 page  
AT/TSC8x251G2D
Figure 3. TSC80251G2D 44-pin VQFP Package
P1.5/CEX2/MISO
P1.6/CEX3/SCL/SCK/WAIT#
P1.7/A17/CEX4/SDA/MOSI/WCLK
RST
P3.0/RXD
AWAIT#
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
TSC80251G2D
33 P0.4/AD4
32 P0.5/AD5
31 P0.6/AD6
30 P0.7/AD7
29 EA#/VPP
28 NMI
27 ALE/PROG#
26 PSEN#
25 P2.7/A15
24 P2.6/A14
23 P2.5/A13
4135F–8051–11/06
5
Free Datasheet http://www.datasheet4u.net/
5 Page 
AT/TSC8x251G2D
Address Spaces
Program/Code Memory
The TSC80251G2D derivatives implement four different address spaces:
• On-chip ROM program/code memory (not present in ROMless devices)
• On-chip RAM data memory
• Special Function Registers (SFRs)
• Configuration array
The TSC83251G2D and TSC87251G2D implement 32 KB of on-chip program/code
memory. Figure 4 shows the split of the internal and external program/code memory
spaces. If EA# is tied to a high level, the 32-Kbyte on-chip program memory is mapped
in the lower part of segment FF: where the C251 core jumps after reset. The rest of the
program/code memory space is mapped to the external memory. If EA# is tied to a low
level, the internal program/code memory is not used and all the accesses are directed to
the external memory.
The TSC83251G2D products provide the internal program/code memory in a masked
ROM memory while the TSC87251G2D products provide it in an EPROM memory. For
the TSC80251G2D products, there is no internal program/code memory and EA# must
be tied to a low level.
Figure 4. Program/Code Memory Mapping
Program/code
Program/code
External Memory Space
Segments
32 KB
32 KB
EA# = 0
FF:FFFFh
FF:8000h
FF:7FFFh
FF:0000h
FE:FFFFh
EA# = 1
On-chip ROM/EPROM
Code Memory
32 KB
64 KB
FE:0000h
FD:FFFFh
Reserved
02:0000h
01:FFFFh
128 KB
01:0000h
00:FFFFh
4135F–8051–11/06
00:0000h
Note:
Special care should be taken when the Program Counter (PC) increments:
If the program executes exclusively from on-chip code memory (not from external mem-
ory), beware of executing code from the upper eight bytes of the on-chip ROM
(FF:7FF8h-FF:7FFFh). Because of its pipeline capability, the TSC80251G2D derivative
may attempt to prefetch code from external memory (at an address above FF:7FFFh)
and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these 8 bytes does
not affect Ports 0 and 2.
When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for
11
Free Datasheet http://www.datasheet4u.net/
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