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EV10AQ190 fiches techniques PDF

e2v - Low power QUAD 10-bit 1.25 Gsps ADC operating up to 5 Gsps

Numéro de référence EV10AQ190
Description Low power QUAD 10-bit 1.25 Gsps ADC operating up to 5 Gsps
Fabricant e2v 
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EV10AQ190 fiche technique
EV10AQ190
Datasheet - Preliminary
EV10AQ190
Low power QUAD 10-bit 1.25 Gsps ADC
operating up to 5 Gsps
Main Features
ƒ Quad ADC with 10-bit resolution using true e2v single core technology
1.25 Gsps Sampling Rate in 4-channel mode
2.5 Gsps Sampling Rate in 2-channel mode
5 Gsps Sampling Rate in 1-channel mode
Built-in four-by-four Cross Point Switch
ƒ Single 2.5 GHz Differential Symmetrical Input Clock
ƒ 500 mVpp Analog Input (Differential AC or DC Coupled)
ƒ ADC Master Reset (LVDS)
ƒ Double Data Rate Output Protocol
ƒ LVDS Output format
ƒ Digital Interface (SPI) with Reset Signal:
Channel Mode Selection
Selectable bandwidth (2 available settings)
Gain, Offset, Phase Control
Standby Mode (full or partial)
Binary or Gray Coding Selection
Test Modes (ramp, flashing “1”)
ƒ Power Supplies: single 3.3V (1.8V Outputs)
ƒ Reduced clock induced transients on power supply pins due to BiCMOS Silicon technology
ƒ Power Dissipation: 1.4W per channel
ƒ EBGA380 Package (RoHS, 1.27 mm Pitch)
Performance
ƒ Selectable Full Power Input Bandwidth (-3 dB) up to 3 GHz (4-2-1 channel mode)
ƒ Band flatness: ± 0.5 dB from DC to 30% of full Power Input bandwidth
ƒ Channel-To-Channel Isolation: > 60 dB
ƒ 4-channel mode (Fsampling = 1.25 Gsps, -1 dBFS)
ENOB = 8.8 bit, SFDR = 65 dBc, SNR = 56 dB, DNL = ±0.3 LSB, INL = ±1.5 LSB (Fin= 100 MHz)
ENOB = 8.5 bit, SFDR = 63 dBc, SNR = 54 dB (Fin= 620 MHz)
ENOB = 7.8 bit, SFDR = 57 dBc, SNR = 50 dB (Fin= 1.2 GHz)
ƒ 2-channel mode or 1-channel mode (Fsampling = 2.5 Gsps and 5 Gsps respectively)
ENOB = 8.7 bit, SFDR = 63 dBc, SNR = 56 dB, DNL = ±0.3 LSB, INL = ±1.5 LSB (Fin= 100 MHz)
ENOB = 8.4 bit, SFDR = 61 dBc, SNR = 54 dB (Fin= 620 MHz)
ENOB = 7.7 bit, SFDR = 55 dBc, SNR = 50 dB (Fin= 1.2 GHz)
ƒ BER: 10-16 at Full speed
ƒ Band flatness: ± 0.5 dB from DC to 30% of full Power Input bandwidth
ƒ Low pipe line delay: 4-channel: 9 cycles, 2-channel:9-10 cycles, -channel: 8.5-10 cycles
1
BDC-10/09 – Preliminary
e2v semiconductors SAS 2009
e2v reserves the right to change or modify specifications and features without notice at any time
Free Datasheet http://www.datasheet-pdf.com/

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