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PDF AL1101 Data sheet ( Hoja de datos )
| Número de pieza | AL1101 | |
| Descripción | stereo ADC | |
| Fabricantes | Alesis | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AL1101 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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General Description
The AL1101 stereo ADC is a high
performance 24-bit analog to digital audio
converter. Dynamic range is 107dB (A-
weighted). The sensible pinout and easy
user interface are unprecedented. The
part has an internal high quality phase-
locked loop that eliminates the need for
external high frequency clocks.
Features
G 24 bit conversion
G 107dB dynamic range (A-wt)
G .002% THD (input=-1dBFS)
G 64X oversampling, 5th order 1 bit ∆-Σ
modulator
G 64:1 linear phase digital decimation
filter
G sample rate variable from 24kHz to
55kHz
G digital high-pass filter
G total power consumption 110mW
(Fs=48kHz)
G internal PLL derives all necessary
timing signals from one external Fs
clock
G serial output bit-rate selectable 32/24
bits/frame
G full scale differential input =+/-4V
([IN+]-[IN-])
G 5V operation
INL+
INL-
AGND
INR+
INR-
MID
REF+
REF-
VA
AGND
VD
DGND
DGND
DOUT
FORMAT
WDCLK
16 pin SOIC
150 mils wide
Alesis Semiconductor
DS1101-1000
12509 Beatrice Street
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551
www.alesis-semi.com
.
Free Datasheet http://www.Datasheet4U.com
1 page  
System Description
Serial Interface and Timing
The AL1101 presents its 2’s complement
serial data in a standard MSB-first format.
Two bit-rates are provided. The 32-
bits/frame rate (FORMAT low) is suitable for
use in systems where 256 Fs master clocks
are present. The 24-bits/frame rate
(FORMAT high) is convenient when
interfacing with circuits where 384 Fs
master clocks are present.
The output sample period is defined between
rising edges of wordclock (WDCLK) input.
Nominally, this is a 50% duty-cycle clock at
frequency Fs, but it can be a pulse with
Ts/256 < pulse-width < Ts (255/256);
Ts=1/Fs. Left channel data output starts
when WDCLK rises and right channel data
output starts Ts/2 seconds later (when
WDCLK falls if 50% duty cycle).
The serial bits are output on the rising edge
of an internally generated bit clock (rising
edge aligned with rising edge of WDCLK)
that runs at 64Fs when FORMAT is low (32
bits/frame), or 48Fs when FORMAT is high
(24 bits/frame). The data is valid +/-100ns
from the center of these bit-frames. See
timing diagram on next page.
Input Logic Levels
The AL1101 can properly receive input
logical ‘1’ voltages of .55VD. This means the
AL1101 can interface directly with logic
signals supplied from 3.3V systems. No
special interface circuitry is required.
Internal Phase-Locked Loop (PLL)
The AL1101 contains an internal PLL that
locks to the rising edge of WDCLK and
produces all necessary high frequency
clocks and timing signals to operate the
device. This high quality PLL will reject any
high-frequency jitter on the incoming
wordclock (jitter rejection corner approx.
4kHz).
The PLL allows a simplified user interface
and eliminates the need of running high
frequency clocks on PCB traces to the part.
This reduces unwanted RF noise and
coupling problems that can occur when
these clocks are required as input pins for a
device.
Digital High Pass
The AL1101 has an internal 2.5Hz single
pole digital filter. The filter removes any
offset present in the internal amplifiers and
prevents DC codes from appearing at the
data outputs. The response of the filter is
-.067dB at 20Hz.
Alesis Semiconductor
DS1101-1000
12509 Beatrice Street
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
-5-
.
Free Datasheet http://www.Datasheet4U.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AL1101.PDF ] | |
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