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PDF ADD5201 Data sheet ( Hoja de datos )

Número de pieza ADD5201
Descripción White LED Driver
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
High Efficiency, Eight-String, White LED
Driver for LCD Backlight Applications
ADD5201
FEATURES
White LED driver based on inductive boost converter
Integrated 50 V MOSFET with 2.9 A peak current limit
Input voltage range: 6 V to 21 V
Maximum output adjustable up to 45 V
350 kHz to 1 MHz adjustable operating frequency
Built-in soft start for boost converter
Drives up to eight LED current sources
LED current adjustable up to 30 mA for each channel
Headroom control to maximize efficiency
Adjustable output dimming frequency: 200 Hz to 10 kHz
LED open/short fault protection
Selectable brightness control interface modes
PWM input
SMBus serial interface
Selectable dimming controls
Fixed delay PWM dimming control with 8-bit resolution
No delay PWM dimming control with 8-bit resolution
Phase shift PWM dimming control with 8-bit resolution
Direct PWM dimming control
DC current dimming mode with 8-bit resolution
General
Thermal shutdown
Undervoltage lockout
28-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Notebook PCs, UMPCs, and monitor displays
GENERAL DESCRIPTION
The ADD5201 is a white LED driver for backlight applications
based on high efficiency, current mode, step-up converter tech-
nology. It is designed with a 0.15 Ω, 2.9 A internal switch and a
pin adjustable operating frequency between 350 kHz and 1 MHz.
The ADD5201 contains eight regulated current sources for
uniform brightness intensity. Each current source can be
driven up to 30 mA.
The ADD5201 drives up to eight parallel strings of multiple
series connected LEDs with a ±1.5% current regulation accuracy.
The device provides an adjustable LED driving current up to
30 mA for each channel by an external resistor. The ADD5201
provides various brightness control methods. The LED dimming
control can be achieved through SMBus and/or pulse-width
modulation (PWM) input. Each dimming mode is selectable
BLOCK DIAGRAM
STEP-UP SWITCHING REGULATOR
EIGHT CURRENT SOURCES
INTERFACE
8-BIT DIMMING CONTROL LOGIC
UNDERVOLTAGE LOCKOUT
SOFT START
THERMAL PROTECTION
OVERVOLTAGE PROTECTION
AUTODISABLE FOR LED OPEN/SHORT
Figure 1.
with two external dimming mode selection pins. The device pro-
vides a pin adjustable output dimming frequency range from
200 Hz to 10 kHz.
The ADD5201 operates over an input voltage range of 6 V to
21 V, but the device can function with a voltage as low as 5.4 V.
The ADD5201 has multiple safety protection features to prevent
damage during fault conditions. If any LED is open or short, the
device automatically disables the faulty current regulator. The
internal soft start prevents inrush current during startup. A
thermal shutdown protection prevents thermal damage.
The ADD5201 is available in a low profile, thermally enhanced,
4 mm × 4 mm × 0.75 mm, 28-lead, RoHS compliant lead frame
chip scale package (LFCSP) and is specified over the industrial
temperature range of −25°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
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ADD5201 pdf
Data Sheet
SMBus SPECIFICATIONS
Table 3.
Parameter1
SMBus INTERFACE
Data, Clock Input Low Level
Data, Clock Input High Level
Data, Clock Output Low Level
SMBus TIMING SPECIFICATIONS
Clock Frequency
Bus-Free Time Between Stop and Start Conditions
Hold Time After Start Condition2
Setup Time
Repeated Start Condition
Stop Condition
Data
Data Hold Time
Clock Period
Low
High
Clock/Data
Fall Time
Rise Time
1 These specifications are guaranteed by design.
2 After this period, the first clock is generated.
GENERAL SPECIFICATIONS
Table 4.
Parameter
SUPPLY
Input Voltage Range
Quiescent Current
Shutdown Supply Current
VDDIO REGULATOR
Regulated Output
Short-Circuit Current
PWM INPUT
Voltage
High
Low
Allowable Input Range
THERMAL SHUTDOWN
Threshold1
Hysteresis1
UVLO
VIN Threshold
Falling
Rising
SHDN CONTROL
Input Voltage
Low
High
Input Current
1 This specification is guaranteed by design.
Symbol
VIN
IQ
ISD
VVDDIO_REG
IVDDIO_SC
VPWM_HIGH
VPWM_LOW
TSD
TSDHYS
VUVLOF
VUVLOR
VIL
VIH
ISHDN
ADD5201
Symbol
VIL
VIH
VOL
fSMB
tBUF
tHD; STA
tSU; STA
tSU; STO
tSU; DAT
tHD; DAT
tLOW
tHIGH
tF
tR
Min Typ Max Unit
0.5 V
2.2 5.5 V
0.8 V
10 100 kHz
4.7 µs
4.0 µs
4.7 µs
4.0 µs
250 ns
300 ns
4.7 µs
4.0 50 μs
300 ns
1 μs
Test Conditions/Comments
6 V ≤ VIN ≤ 21 V, SHDN = high
6 V ≤ VIN ≤ 21 V, SHDN = low
6 V ≤ VIN ≤ 21 V
6 V ≤ VIN ≤ 21 V
Min Typ Max
6 21
2.5 5.0
40 160
3.2 3.3 3.4
2.3 5.0
Unit
V
mA
µA
V
mA
2.2 5.5 V
0.8 V
200 10,000 Hz
160 °C
30 °C
VIN falling
VIN rising
4.4 4.6
5.0 5.4
V
V
SHDN = 3.3 V
2.0
6
1.0
V
V
µA
Rev. A | Page 5 of 20
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ADD5201 arduino
Data Sheet
BACKLIGHT BRIGHTNESS CONTROL
The ADD5201 mode of operation is selectable between the
SMBus serial input and/or external PWM input. The LED
brightness control method follows the method for selecting the
mode of operation. For correct operation of the ADD5201, set
the SEL1 and SEL2 mode selection pins based on the application
conditions (see Table 9).
Table 9. Brightness Control Mode Selection
Mode Selection Settings
SEL1
SEL2
Dimming Mode
High
High
Fixed delay PWM
High
Open
Phase shift PWM
High
Low
No delay PWM
Open
High
Fixed delay PWM
Open
Open
Phase shift PWM
Open
Low
No delay PWM
Low
High
DC current
Low
Open
DC current
Low Low Direct PWM
Interface
SMBus
SMBus
SMBus
PWMI
PWMI
PWMI
SMBus
PWMI
PWMI
PWM DIMMING MODE
The fPWM duty is internally generated by 256 steps through the
PWM input duty and/or the SMBus register setting value in the
fPWM duty range of 0% to 100%. Nevertheless, each current source
has a minimum on time requirement for the LED current regu-
lation such that the dimming is in the range of 3% to 100%
when fPWM is 5 kHz and when the boost converter switching
frequency is in the range of 1 MHz to 600 kHz. In addition, the
brightness controllable range is from 5% to 100% when the
boost converter switching frequency is in the range of 350 kHz
to 600 kHz.
Note that the ADD5201 has immunity when the PWM input
duty cycle is converted to 256 steps even when the PWM input
has ±0.195% jitter.
Fixed Delay PWM
Fixed delay PWM mode is selected when SEL1 = open and
SEL2 = high for a PWMI application, or when SEL1 = high and
SEL2 = high for an SMBus application. In fixed delay PWM
mode, each current source has a fixed time delay from when the
current source turns on and off with respect to the preceding
current source. The fixed delay time is set by fPWM. Each channel
delay time is set by the following equation:
tD
=
2 × t FPWM
256
where tFPWM = 1/fPWM, and fPWM is the LED dimming frequency.
ADD5201
DUTY = 60%
PWMI
fPWM
tFPWM
(DUTY = 60%)
tOFF
tON
ILED1
tD
ILED2
ILED8 7 × tD
Figure 17. Fixed Delay PWM Dimming Timing
Phase Shift PWM
The phase shift PWM mode is selected when SEL1 = open and
SEL2 = open for a PWMI application, or when SEL1 = high and
SEL2 = open for an SMBus application. In the phase shift PWM
mode, each current source phase delay is programmed by the
number of current sources in operation and the fPWM cycle. Each
current source delay time is calculated by the following equation:
tD
=
t FPWM
N
where:
N is the number of operating current sources.
tFPWM is the fPWM cycle.
PWMI
DUTY = 75%
tFPWM
(DUTY = 75%)
fPWM
ILED1
ILED2
tON tOFF
tD
ILED3
tD
ILED4
tD
ILED5
tD
ILED6
tD
ILED7
tD
ILED8
tD
tD
Figure 18. Phase Shift PWM Dimming Timing
No Delay PWM
The no delay PWM mode is selected when SEL1 = open and
SEL2 = low for a PWMI application, or when SEL1 = high and
SEL2 = low for an SMBus application. In the no delay PWM
mode, all operating current sources turn on and off at the same
time without any phase delay.
Rev. A | Page 11 of 20
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