|
|
PDF AT45DQ161 Data sheet ( Hoja de datos )
| Número de pieza | AT45DQ161 | |
| Descripción | 16-Mbit DataFlash 2.3V or 2.5V Minimum SPI Serial Flash Memory | |
| Fabricantes | ADESTO | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AT45DQ161 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
AT45DQ161
16-Mbit DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V or 2.5V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports RapidS™ operation
Supports Dual-input and Quad-input Buffer Write
Supports Dual-output and Quad-output Read
Very high operating frequencies
85MHz (for SPI)
85MHz (for Dual-I/O and Quad-I/O)
Clock-to-output time (tV) of 6ns maximum
User configurable page size
512 bytes per page
528 bytes per page (default)
Page size can be factory pre-configured for 512 bytes
Two fully independent SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the main memory array
Flexible programming options
Byte/Page Program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible erase options
Page Erase (512/528 bytes), Block Erase (4KB)
Sector Erase (128KB), Chip Erase (16-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Hardware and software controlled reset options
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
500nA Ultra-Deep Power-Down current (typical)
3µA Deep Power-Down current (typical)
25µA Standby current (typical)
11mA Active Read current (typical at 20MHz)
Endurance: 100,000 program/erase cycles per page minimum (50,000 cycles
for extended temperature option)
Data retention: 20 years
Complies with full industrial temperature range (extended temperature optional)
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150" wide and 0.208" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Ultra-thin UBGA (6 x 6 x 0.6mm)
8790B–DFLASH–10/2013
http://www.Datasheet4U.com
1 page  
2. Block Diagram
Figure 2-1. Block Diagram
WP (I/O2)
Page (512/528 bytes)
Flash Memory Array
Buffer 1 (512/528 bytes)
Buffer 2 (512/528 bytes)
SCK
CS
RESET (I/O3)
VCC
GND
I/O Interface
SI (I/O0)
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
SO (I/O1)
AT45DQ161 [PRELIMINARY DATASHEET]
8790B–DFLASH–10/2013
5
5 Page 
5.8 Dual-output Read Array
The Dual-output Read Array command is similar to the Continuous Array Read command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting
address has been specified. Unlike the Continuous Array Read command however, the Dual-output Read Array
command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-output Read Array command can be used at any clock frequency up to the maximum specified by fSCK. To
perform a Dual-output Read Array using the standard DataFlash page size (528 bytes), the CSpin must first be asserted,
and then an opcode of 3Bh must be clocked into the device followed by three address bytes and one dummy byte. The
first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory array to read and the
last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page.
To perform a Dual-output Read Array using the binary page size (512 bytes), the opcode 3Bh must be clocked into the
device followed by three address bytes (A20 - A0) and one dummy byte.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the I/O1 and I/O0 pins. The data is always output with the MSB of a byte first, and the MSB is always
output on the I/O1 pin. During the first clock cycle, bit seven of the first data byte will be output on the I/O1 pin while bit six
of the same data byte will be output on the I/O0 pin. During the next clock cycle, bits five and four of the first data bytewill
be output on the I/O1 and I/O0 pins, respectively. The sequence continues with each byte of data being output after every
four clock cycles.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of
data. When the end of a page in the main memory is reached during a Dual-output Read Array the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state both the I/O1 and I/O0 pins. The Dual-
output Dual-output Read Array bypasses both data buffers and leaves the contents of the buffers unchanged.
5.9 Quad-output Read Array
The Quad-output Read Array command is similar to the Dual-output Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting
address has been specified. Unlike the Dual-output Read Array command however, the Quad-output Read Array
command allows four bits of data to be clocked out of the device on every clock cycle rather than two.
Note: The QE bit in the Configuration Register must be previously set in order for any Quad-I/O command (i.e.
Quad-output Read Array command) to be enabled and for the RESET and WP pins to be converted to I/O
data pins.
The Quad-output Read Array command can be used at any clock frequency up to the maximum specified by fSCK. To
perform a Quad-output Read Array using the standard DataFlash page size (528 bytes), the CS pin must first be
asserted, and then an opcode of 6Bh must be clocked into the device followed by three address bytes and one dummy
byte. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory array to read
and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page.
To perform a Quad-output Read Array using the binary page size (512 bytes), the opcode 6Bh must be clocked into the
device followed by three address bytes (A20 - A0) and one dummy byte.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always output on the I/O3
pin. During the first clock cycle, bit seven of the first data byte will be output on the I/O3 pin while bits six, five, and four of
the same data byte will be output on the I/O2, I/O1, and I/O0 pins, respectively. During the next clock cycle, bits three,
two, one, and zero of the first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively. The sequence
continues with each byte of data being output after every two clock cycles.
AT45DQ161 [PRELIMINARY DATASHEET]
8790B–DFLASH–10/2013
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT45DQ161.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AT45DQ161 | 16-Mbit DataFlash 2.3V or 2.5V Minimum SPI Serial Flash Memory | ADESTO |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |