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PDF NB3V8312C Data sheet ( Hoja de datos )
| Número de pieza | NB3V8312C | |
| Descripción | Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB3V8312C
Ultra-Low Jitter, Low Skew
1:12 LVCMOS/LVTTL Fanout
Buffer
The NB3V8312C is a high performance, low skew L VCMOS
fanout buffer which can distribute 12 ultra −low jitter clocks from an
LVCMOS/LVTTL input up to 250 MHz.
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The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tri−stated) via the OE input, or enabled when High.
The NB3V8312C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW , potential output glitching or
runt pulse generation is eliminated.
LQFP−32
FA SUFFIX
CASE 873A
1 32
QFN32
MN SUFFIX
CASE 488AM
Separate V DD core and V DDO output supplies allow the output
buffers to operate at the same supply as the V DD (VDD = V DDO) or
from a lower supply voltage. Compared to single −supply operation,
VDDO
VDD
GND
Q0
dual supply operation enables lower power consumption and
output−level compatibility.
The VDD core supply voltage can be set to 3.3 V , 2.5 V or 1.8 V,
while the VDDO output supply voltage can be set to 3.3 V , 2.5 V, or
1.8 V, with the constraint that VDD ≥ VDDO.
This buffer is ideally suited for various networking, telecom, server
CLK_EN
RPU
D
Q
Q1
Q2
Q3
Q4
and storage area networking, RRU LO reference distribution, medical
and test equipment applications.
Features
• Power Supply Modes:
CLK
RPD
Q5
Q6
Q7
VDD (Core) / VDDO (Outputs)
3.3 V
/ 3.3 V
3.3 V
/ 2.5 V
3.3 V
/ 1.8 V
Q8
Q9
Q10
2.5 V
2.5 V
1.8 V
/ 2.5 V
/ 1.8 V
/ 1.8 V
RPU
OE
Q11
• 250 MHz Maximum Clock Frequency
Figure 1. Simplified Logic Diagram
• Accepts LVCMOS, LVTTL Clock Inputs
• LVCMOS Compatible Control Inputs
• 12 LVCMOS Clock Outputs
• Synchronous Clock Enable
ORDERING AND MARKING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
• Output Enable to High Z State Control
• 150 ps Max. Skew Between Outputs
• Temp. Range −40°C to +85°C
• 32−pin LQFP and QFN Packages
Applications
• Networking
• Telecom
• Storage Area Network
• These are Pb−Free Devices
End Products
• Servers
• Routers
• Switches
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 0
1
Publication Order Number:
NB3V8312C/D
http://www.Datasheet4U.com
1 page  
NB3V8312C
Table 5. LVCMOS/LVTTL DC CHARACTERISTICS (TA = −40°C to +85°C)
Symbol
Characteristics
Conditions
Min Typ Max Unit
VDD = 3.465 V
2.0
VDD +
0.3
V
VIH Input High Voltage
VDD = 2.625 V
1.7
V0D.D3 +
V
VIL Input Low Voltage
IIH
Input High
Current
CLK
OE, CLK_EN
VDD = 2.0 V
VDD = 3.465 V
VDD = 2.625 V
VDD = 2.0 V
VDD = VIN = 3.465 V or 2.625 V or 2.0 V
0.65 x
VDD
−0.3
−0.3
−0.3
VDD +
0.3
1.3
0.7
0.35 x
VDD
150
5
V
V
V
V
mA
IIL
Input Low
Current
CLK
OE, CLK_EN
VDD = 3.465 V or 2.625 V or 2.0 V, VIN = 0 V
−5
−150
mA
VOH Output High Voltage (Note 6)
VDDO = 3.3 V ±5%
VDDO = 2.5 V ±5%
VDDO = 2.5 V ±5%; IOH = −1 mA
VDDO = 1.8 V ±0.2 V
2.6
1.8
2.0
VDD –
0.4
V
VDDO = 1.8 V ±0.2 V; IOH = −100 mA
VDD –
0.2
VOL Output Low Voltage (Note 6)
VDDO = 3. 3V ±5%
VDDO = 2.5 V ±5%
VDDO = 2.5 V ±5%; IOL = 1 mA
VDDO = 1.8 V ±0.2 V
VDDO = 1.8 V ±0.2 V; IOL = 100 mA
0.5
0.45
0.4 V
0.35
0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to VDDO/2 unless otherwise specified. See Figure 7.
Table 6. POWER SUPPLY DC CHARACTERISTICS, (TA = −40°C to +85°C)
VDD (Core)
VDDO (Outputs)
3.3 V ±5%
3.3 V ±5%
3.3 V ±5%
2.5 V ±5%
3.3 V ±5%
1.8 V ± 0.2V
2.5 V ±5%
2.5 V ±5%
2.5 V ±5%
1.8 V ± 0.2V
1.8 V ± 0.2 V
1.8 V ± 0.2V
Min Typ Max Unit
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
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5
5 Page 
NB3V8312C
PACKAGE DIMENSIONS
PIN ONE
LOCATION
ÉÉÉÉD
QFN32 5x5, 0.5P
CASE 488AM
ISSUE O
A
B
E
2 X 0.15 C
TOP VIEW
2 X 0.15 C
0.10 C
32 X 0.08 C
(A3)
SIDE VIEW A1
A
SEATING
PLANE
C
L
32 X
EXPOSED PAD
9
D2
16 17
K
32 X
8
E2
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN NOM MAX
A 0.800 0.900 1.000
A1 0.000 0.025 0.050
A3 0.200 REF
b 0.180 0.250 0.300
D 5.00 BSC
D2 2.950 3.100 3.250
E 5.00 BSC
E2 2.950 3.100 3.250
e 0.500 BSC
K 0.200 −−− −−−
L 0.300 0.400 0.500
SOLDERING FOOTPRINT*
5.30
32 X
0.63
3.20
1
32
32 X b
0.10 C A B
0.05 C
24
25
e
BOTTOM VIEW
3.20 5.30
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semi conductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB3V8312C/D
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| PDF Descargar | [ Datasheet NB3V8312C.PDF ] | |
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