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PDF ISL6363 Data sheet ( Hoja de datos )
| Número de pieza | ISL6363 | |
| Descripción | Multiphase PWM Regulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Multiphase PWM Regulator for VR12™ Desktop CPUs
ISL6363
Fully compliant with VR12™ specifications, the ISL6363
provides a complete solution for microprocessor core and
graphics power supplies. It provides two Voltage Regulators
(VRs) with three integrated gate drivers. The first output (VR1)
can be configured as a 4, 3, 2 or 1-phase VR while the second
output (VR2) is a 1-phase VR. The two VRs share a serial control
bus to communicate with the CPU and achieve lower cost and
smaller board areacomparedwith a two-chip approach.
Based on Intersil’s Robust Ripple Regulator R3 Technology™,
the PWM modulator, compared to traditional modulators, has
faster transient settling time, variable switching frequency
during load transients and has improved light load efficiency
with its ability to automatically change switching frequency.
The ISL6363 has several other key features. Both outputs
support DCR current sensing with a single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. Both outputs come with remote voltage sensing,
programmable VBOOT voltage, serial bus address, IMAX, TMAX,
adjustable switching frequency, OC protection and separate
power-good indicators. To reduce output capacitors, the
ISL6363 also has an additional compensation function for
PS1/2 mode and high frequency load transient compensation.
Features
• Serial Data Bus (SVID)
•D ual Outputs:
- Configurable 4, 3, 2 or 1-phase for the 1st Output with 2
Integrated Gate Drivers
- 1-phase for the 2nd Output with Integrated Gate Driver
• Precision Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• PS2 Compensation and High Frequency Load Transient
Compensation
• Differential Remote Voltage Sensing
• Lossless Inductor DCR Current Sensing
•P rogrammable VBOOT Voltage at Start-up
• Resistor Programmable Address, IMAX, TMAX for Both
Outputs
• Adaptive Body Diode Conduction Time Reduction
Applications
•V R12 Desktop Computers
Related Literature
• ISL6363EVAL1Z User Guide
VCORE
50mV/DIV
COMP
1V/DIV
2µs/DIV
65A STEP LOAD
1V/DIV
FIGURE 1. FAST TRANSIENT RESPONSE
1.15
1.10
1.05
1.00
0.95
1.7mΩ LOADLINE
1.1V - PS1
1.1V - PS0
0.90
0 5 101 5 20 253 03 5 40 45 50 55 60 65 70 75 80 85
IOUT (A)
FIGURE 2. ACCURATE LOADLINE, VCORE vs IOUT
September 29, 2011
FN6898.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
http://www.Datasheet4U.com
1 page  
Block Diagram
ISL6363
VWG
COMPG
RTNG
FBG
ISUMPG
ISUMNG
COMPG
+
+Σ
+
E/A
_
IDROOPG
+
CURRENT
_ SENSE
VR2
MODULATOR
IMONG
NTCG
NTC
VR_HOT#
ADDR
VR_ON
SDA
ALERT#
SCLK
VW
COMP
RTN
FB
PSICOMP
ISUMP
ISUMN
ISEN4
ISEN3
ISEN2
ISEN1
VSEN
TEMP
MONITOR
T_MONITOR
IMAX
VBOOT
TMAX
SET (A/D)
ADDR
DIGITAL
INTERFACE
COMPG
COMP
A/D
D/A
MODE
IMONG
IMON
DAC2
DAC1
MODE2
MODE1
VREADY
COMP
PSICOMP
CIRCUIT
+
_
+
+Σ
+
E/A
_
IDROOP
CURRENT
SENSE
OC FAULT
OV FAULT
VR1
MODULATOR
CURRENT
BALANCING
IMON
GND
OC FAULT
IBAL FAULT
OV FAULT
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
DRIVER
5
BOOTG
UGATEG
PHASEG
LGATEG
PGOODG
VCC
PVCCG
PVCC
SCOMP
PWM4
PWM3
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
PGOOD
FN6898.0
September 29, 2011
5 Page 
ISL6363
Gate Driver Timing Diagram
PWM
UGATE
tLGFUGR
tRU
tFU
1V
LGATE
tFL
1V
tUGFLGR
tRL
Theory of Operation
Multiphase R3 Modulator
The ISL6363 is a multiphase regulator implementing Intel’s™
VR12™ protocol. It has two voltage regulators, VR1 and VR2, on
one chip. VR1 can be programmed for 1, 2, 3, or 4-phase
operation, and VR2 is dedicated for 1-phase operation. The
following description is based on VR1, but also applies to VR2
because the same architecture is implemented.
The ISL6363 uses Intersil’s patented R3 (Robust Ripple Regulator)
modulator. The R3 modulator combines the best features of fixed
frequency PWM and hysteretic PWM while eliminating many of
their shortcomings. Figure 3 conceptually shows the multiphase
R3 modulator circuit, and Figure 4 shows the operation principles.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor Crm with a current source equal to
gmVo, where gm is a gain factor. Crm voltage Vcrm is a sawtooth
waveform traversing between the VW and COMP voltages. It resets
to VW when it hits COMP, and generates a one-shot master clock
signal. A phase sequencer distributes the master clock signal to
the slave circuits. If VR1 is in 4-phase mode, the master clock
signal will be distributed to the four phases, and the Clock1~4
signals will be 90° out-of-phase. If VR1 is in 3-phase mode, the
master clock signal will be distributed to the three phases, and the
Clock1~3 signals will be 120° out-of-phase. If VR1 is in 2-phase
mode, the master clock signal will be distributed to Phases 1 and 2,
and the Clock1 and Clock2 signals will be 180° out-of-phase. If
VR1 is in 1-phase mode, the master clock signal will be distributed
to Phase 1 only and be the Clock1 signal.
VW MASTER CLOCK CIRCUIT
MASTER
MASTER COMP
CLOCK Vcrm
CLOCK Phase
Sequencer
gmVo
Crm
Clock1
Clock2
Clock3
VW
Vcrs1
Crs1
VW
Vcrs2
Crs2
VW
Vcrs3
Crs3
SLAVE CIRCUIT 1
Clock1
S
R
Q
PWM1 Phase1
L1
IL1
gm
SLAVE CI RCUIT 2
Clock2
S
R
Q
PWM2 Phase2
L2
IL2
gm
SLAVE CIRCUIT 3
Clock3
S
R
Q
PWM3 Phase3
L3
IL3
gm
Vo
Co
FIGURE 3. R3 MODULATOR CIRCUIT
Each slave circuit has its own ripple capacitor Crs, whose voltage
mimics the inductor ripple current. A gm amplifier converts the
inductor voltage into a current source to charge and discharge
Crs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges Crs. When Crs
voltage VCrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
11 FN6898.0
September 29, 2011
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet ISL6363.PDF ] | |
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