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PDF N25Q00AA Data sheet ( Hoja de datos )
| Número de pieza | N25Q00AA | |
| Descripción | NOR Flash Memory | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
Micron Serial NOR Flash Memory
3V, Multiple I/O, 4KB Sector Erase
N25Q00AA
Features
• Stacked device (four 256Mb die)
• SPI-compatible serial bus interface
• Double transfer rate (DTR) mode
• 2.7–3.6V single supply voltage
• 108 MHz (MAX) clock frequency supported for all
protocols in single transfer rate (STR) mode
• 54 MHz (MAX) clock frequency supported for all
protocols in DTR mode
• Dual/quad I/O instruction provides increased
throughput up to 54 MB/s
• Supported protocols
– Extended SPI, dual I/O, and quad I/O
– DTR mode supported on all
• Execute-in-place (XIP) mode for all three protocols
– Configurable via volatile or nonvolatile registers
– Enables memory to work in XIP mode directly af-
ter power-on
• PROGRAM/ERASE SUSPEND operations
• Available protocols
– Available READ operations
– Quad or dual output fast read
– Quad or dual I/O fast read
• Flexible to fit application
– Configurable number of dummy cycles
– Output buffer configurable
• Software reset
• 3-byte and 4-byte addressability mode supported
• 64-byte, user-lockable, one-time programmable
(OTP) dedicated area
• Erase capability
– Subsector erase 4KB uniform granularity blocks
– Sector erase 64KB uniform granularity blocks
– Single die erase (32MB)
• Write protection
– Software write protection applicable to every
64KB sector via volatile lock bit
– Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2,
BP3, and TB)
– Additional smart protections, available upon re-
quest
• Electronic signature
– JEDEC-standard 2-byte signature (BA21h)
– Unique ID code (UID): 17 read-only bytes,
including: Two additional extended device ID
bytes to identify device factory options; and cus-
tomized factory data (14 bytes)
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages – JEDEC-standard, all RoHS-compliant
– L-PBGA-24b05/6mm x 8mm ( also known as
LBGA24 )
– SOP2-16/300 mils (also known as SO16W, SO16-
Wide, SOIC-16 )
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
http://www.Datasheet4U.com
1 page  
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Features
List of Tables
Table 1: Signal Descriptions ............................................................................................................................. 9
Table 2: Sectors[2047:0] ................................................................................................................................. 12
Table 3: Data Protection Using Device Protocols ............................................................................................. 13
Table 4: Memory Sector Protection Truth Table .............................................................................................. 13
Table 5: Protected Area Sizes – Upper Area ..................................................................................................... 14
Table 6: Protected Area Sizes – Lower Area ...................................................................................................... 14
Table 7: SPI Modes ........................................................................................................................................ 16
Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ 18
Table 9: Status Register Bit Definitions ........................................................................................................... 20
Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... 21
Table 11: Volatile Configuration Register Bit Definitions .................................................................................. 22
Table 12: Sequence of Bytes During Wrap ....................................................................................................... 23
Table 13: Supported Clock Frequencies – STR ................................................................................................. 23
Table 14: Supported Clock Frequencies – DTR ................................................................................................ 23
Table 15: Extended Address Register Bit Definitions ........................................................................................ 25
Table 16: Enhanced Volatile Configuration Register Bit Definitions .................................................................. 25
Table 17: Flag Status Register Bit Definitions .................................................................................................. 26
Table 18: Command Set ................................................................................................................................. 28
Table 19: Lock Register .................................................................................................................................. 36
Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... 38
Table 21: Read ID Data Out ............................................................................................................................ 38
Table 22: Extended Device ID, First Byte ......................................................................................................... 38
Table 23: Serial Flash Discovery Parameter Data Structure .............................................................................. 40
Table 24: Parameter ID .................................................................................................................................. 40
Table 25: Command/Address/Data Lines for READ MEMORY Commands ....................................................... 43
Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address ............................. 44
Table 27: Data/Address Lines for PROGRAM Commands ................................................................................ 54
Table 28: Suspend Parameters ....................................................................................................................... 64
Table 29: Operations Allowed/Disallowed During Device States ...................................................................... 64
Table 30: Reset Command Set ........................................................................................................................ 66
Table 31: OTP Control Byte (Byte 64) .............................................................................................................. 68
Table 32: XIP Confirmation Bit ....................................................................................................................... 71
Table 33: Effects of Running XIP in Different Protocols .................................................................................... 71
Table 34: Power-Up Timing and VWI Threshold ............................................................................................... 74
Table 35: AC RESET Conditions ...................................................................................................................... 75
Table 36: Absolute Ratings ............................................................................................................................. 79
Table 37: Operating Conditions ...................................................................................................................... 79
Table 38: Input/Output Capacitance .............................................................................................................. 79
Table 39: AC Timing Input/Output Conditions ............................................................................................... 80
Table 40: DC Current Characteristics and Operating Conditions ...................................................................... 81
Table 41: DC Voltage Characteristics and Operating Conditions ...................................................................... 81
Table 42: AC Characteristics and Operating Conditions ................................................................................... 82
Table 43: Part Number Information ................................................................................................................ 86
Table 44: Package Details ............................................................................................................................... 87
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
5 Page 
1Gb, 3V, Multiple I/O Serial NOR Flash Memory
Memory Organization
Memory Organization
Memory Configuration and Block Diagram
The memory is a stacked device comprised of four 256Mb chips. Each chip is internally
partitioned into two 128Mb segments. Each page of memory can be individually pro-
grammed. Bits are programmed from one through zero. The device is subsector, sector,
or single 256Mb chip erasable, but not page-erasable. Bits are erased from zero through
one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 sectors (64KB
each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); and 64 OTP
bytes are located outside the main memory array.
Figure 4: Block Diagram
HOLD#
W#/VPP
S#
C
DQ0
DQ1
DQ2
DQ3
Control logic
Address register
and counter
High voltage
generator
64 OTP bytes
I/O shift register
256 byte
data buffer
Status
register
07FFFFFFh
PDF: 09005aef8480cede
n25q_1gb_3V_65nm.pdf - Rev. M 03/14 EN
0000000h
00000FFh
256 bytes (page size)
X decoder
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
11 Page | ||
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