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CT2561
Bus Controller, Remote Terminal and BUS Monitor
FOR MIL-STD-1553B
Features
I Second Source Compatible to the BUS-65610
I 16MHz CT2565 Replacement
I RTU implements all dual redundant mode codes
I Selective mode code illegalization available
I 16 bit microprocessor compatibility
I BC checks status word for correct address and set flags
I RTU illegal mode codes externally selectable
I 16 bit µProcessor compatibility
I DMA handshaking for subsystem message transfers
I Continuous On-Line and Initiated Built-In-Test
I MIL-PRF-38534 compliant circuits available
I Packaging – Hermetic Metal
• 78 Pin, 2.1" x 1.87" x .25" Plug-In type package
• 82 Lead, 2.2" x 1.61" x .18" Flat package
CIRCUIT TECHNOLOGY
www.aeroflex.com
FLEX LA
ISO
9001
CE R T I F I E D
General Description
The CT2561 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller (BC), Remote
Terminal Unit (RTU) and Bus Monitor (MT). Packaged in a hybrid plug-in or flatpack, the CT2561
performs all the functions required to interface a MIL-STD-1553 dual redundant serial data bus such
as ACT4487 and a subsystem parallel three-state data bus.
Using a single Aeroflex custom monolithic ASIC design, the CT2561 features pin-for-pin and
functional CT2565 compatibility, user initiated self-test, and low power consumption.
Compatible with most microprocessors the CT2561 provides a 16bit three-state parallel data bus
and uses direct memory access (DMA type) handshaking for subsystem transfers. All message
transfer timing, DMA and control lines are provided internally, thereby reducing the subsystem
overhead associated with message transfers.
The CT2561 implements all dual redundant MIL-STD-1553 mode codes. In addition, any mode
code may (Optionally) be legalized through the use of an external PROM. Complete error detection
is provided by the CT2561 for BC and RTU operation. Error detection includes: response time-out,
inter-message gaps, sync, parity, Manchester, word count and bit count.
The CT2561 is fully compliant with MIL-STD-1553, is available screened in accordance with the
requirements of MIL-STD-883 and operates over the full military temperature range of -55°C to
+125°C.
eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2561 REV A 8/16/99
Table 1A – Pin Function Table (78 Pin Plug-In) (continued)
Pin #
Symbol
I/O
Description
57
EOM
O End of message output. Logic "0" occurs when BC/RT message is completed.
58 BUFENA I Buffer enable input, may be driven LOW by STATEN or BITEN if subsystem
must read bit or Status words. Enables internal 16 bit bus onto subsystem bus.
59
BUSACK
O Bus acknowledge output. LOW during DMA Handshake, in response to
BUSGRNT.
60
DB1
I/O Bit 1 of 16 bit parallel bus.
61
DB3
I/O Bit 3 of 16 bit parallel bus.
62
DB5
I/O Bit 5 of 16 bit parallel bus.
63
DB7
I/O Bit 7 of 16 bit parallel bus.
64
DB9
I/O Bit 9 of 16 bit parallel bus.
65
DB11
I/O Bit 11 of 16 bit parallel bus.
66
DB13
I/O Bit 13 of 16 bit parallel bus.
67 DB15(MSB) I/O Bit 15 of 16 bit parallel bus.
68
STATERR
O BC output indicates one or more bits set or address mismatch in a received
status word.
69 TXDATA A O Bipolar serial data output to negative input of bus transceiver.
70 RXDATA A I Bipolar serial data input from positive output of bus transceiver.
71
NODT
O No data input. Logic "0" indicates the 1553 bus is idle; HIGH means device front
end is active.
72 RTAD0 I LSB of 5 bit RT address.
73 RTAD2 I Bit 2 of RT address.
74 RTAD4 I Bit 4 of RT address.
75 BCSTRCV O Broadcast receive. Logic "0" means the current command was a broadcast
command.
76 TXDATA B O Bipolar serial output to positive input of bus transceiver.
77 RXDATA B I Bipolar serial input from negative output of bus transceiver.
78
SOM
O Start of message output indicates beginning of RT/BC message transfer
sequence.
Aeroflex Circuit Technology
5 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700