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PDF LTC3618 Data sheet ( Hoja de datos )
| Número de pieza | LTC3618 | |
| Descripción | Dual 4MHz +-3A Synchronous Buck Converter | |
| Fabricantes | Linear Integrated Systems | |
| Logotipo |  |
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LTC3618
Dual 4MHz, ±3A
Synchronous Buck Converter
for DDR Termination
FEATURES
DESCRIPTION
n DDR Power Supply, Termination and Reference
n High Efficiency: Up to 94%
n Dual Outputs with ±3A Output Current Capability
n 2.25V to 5.5V Input Voltage Range
n ±1% Output Voltage Accuracy
n VTT Output Voltage Down to 0.5V
n Shutdown Current ≤1μA
n VTTR = VDDQIN/2, VFB2 = VTTR
n Adjustable Switching Frequency Up to 4MHz
n Internal or External Compensation
n Selectable 0°/90°/180° Phase Shift Between Channels
n Internal or External Soft-Start for VDDQ, Internal
Soft-Start for VTT
n Power Good Status Outputs
n Low Profile 4mm × 4mm QFN-24 and TSSOP-24
Packages
APPLICATIONS
n DDR Memory
n Supports DDR, DDR2, and DDR3 Standards
n Tr acking Supplies
The LTC®3618 is a dual synchronous step-down regulator
using a current mode, constant-frequency architecture. It
provides a complete DDR solution with an input voltage
range from 2.25V to 5.5V.
The output of the first step-down regulator offers a high
accuracy VDDQ supply. A buffered reference generatesTVTR
at 50% of VDDQIN and drives loads up to ±10mA. The
second regulator generates the DDR termination voltage
(VTT) equal to VTTR. Both regulators are capable of deliv-
ering ±3A of load current at 1MHz switching frequency.
The operating frequency is externally programmable up to
4MHz, allowing the use of small sufrace mount inductors.
0°, 90°, or 180° of phase shift between the two channels
can be selected to minimize input current ripple. For
switching noise-sensitive applications, the LTC3618 can
be synchronized to an external clock up to 4MHz.
The LTC3618 is offered in leadless 24-pin 4mm × 4mm
QFN and thermally enhanced 24-pin TSSOP packages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6498466, 6580258, 6611131.
TYPICAL APPLICATION
VIN
3.3V
100μF
392k
VREF
=
VDDQ
2
0.01μF
SVIN
RUN1
PVIN1 PVIN2
VDDQIN
TRACK/SS1
SW1
PGOOD1
ITH1 LTC3618
FB1
RT
MODE/SYNC
PHASE
SW2
RUN2
PGOOD2
FB2
ITH2
VTTR
SGND
PGND
3618 TA01a
1μH
1μH
422k
210k
VDDQ
1.8V/3A
47μF
VTT
0.9V/±3A
47μF
Efficiency and Power Loss vs Load Current
100
90
80
70
60
50
40
30
20
10
0
0.01
VDDQ = 1.8V
VTT = 0.9V
0.1 1
LOAD CURRENT (A)
10
1
0.1
0.01
10
3618 TA01b
3618fb
1
http://www.Datasheet4U.com
1 page  
LTC3618
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 3.3V, f = 1MHz, Figure 3 Circuit,
unless otherwise noted.
Efficiency vs Load Current
100
VMODE/SYNC = SVIN
90
80
70
60
50
40
30
20
10
0
0.01
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
0.1 1
LOAD CURRENT (A)
10
3618 G01
Efficiency vs Load Current
100
VMODE/SYNC = SVIN
90
80
70
60
50
40
30
20
10
0
0.01
VTT = 0.75V
VTT = 0.9V
VTT = 1.25V
0.1 1
LOAD CURRENT (A)
10
3618 G02
Efficiency vs Input Voltage
VDDQ = 1.8V
100
90
80
70
60
50
VMODE/SYNC = SVIN
40
30 ILOAD = 200mA
20
ILOAD = 300mA
ILOAD = 1A
10 ILOAD = 2A
ILOAD = 3A
0
2.25 2.75 3.25 3.75 4.25 4.75 5.25
INPUT VOLTAGE (V)
3618 G03
Efficiency vs Input Voltage
VTT = 0.9V
100
90
80
70
60
50
40
30 ILOAD = 200mA
20
ILOAD = 300mA
ILOAD = 1A
10 ILOAD = 2A
ILOAD = 3A
0
2.25 2.75 3.25 3.75 4.25 4.75 5.25
INPUT VOLTAGE (V)
3618 G04
Forced Continuous Mode
Operation (FCM)
SW1
L1
1A/DIV
SW2
L2
1A/DIV
VDDQ = 1.8V
VTT = 0.9V
NO LOAD
400ns/DIV
3618 G07
VOUT Load Regulation
1.0
0.8
0.6
0.4
VTT = 0.9V
0.2
0 VDDQ = 1.8V
–0.2
–0.4
–0.6
–0.8
–1.0
–3
–2 –1 0
123
LOAD CURRENT (A)
3618 G05
Input Voltage Line Regulation
0.5
0.4
0.3
0.2 VTT = 0.9V
0.1
0 VDDQ = 1.8V
–0.1
–0.2
–0.3
–0.4
–0.5
2.25 2.75 3.25 3.75 4.25 4.75 5.25
INPUT VOLTAGE (V)
3618 G06
Pulse-Skipping Mode
Load Step Transient with
FCM Internal Compensation
VDDQ
200mV/DIV
SW1
L1
1A/DIV
SW2
L2
1A/DIV
IL
2A/DIV
ILOAD
2A/DIV
VDDQ = 1.8V
VTT = 0.9V
NO LOAD
400ns/DIV
3618 G08
VTT IS ALWAYS IN FORCED CONTINUOUS MODE
VIN = 5V
10μs/DIV
VDDQ = 1.8V
ILOAD = 0A TO 3A
3618 G09
3618fb
5
5 Page 
LTC3618
OPERATION
Pulse-Skipping Mode Operation
LTC3618 implements slope compensation by adding a
Connecting the MODE/SYNC pin to SV IN enables pulse- compensation ramp to the inductor current signal.
skipping mode for VDDQ only. As the load current decreases,
the peak inductor current will be determined by the voltage
Short-Circuit Protection
on the ITH1 pin until the ITH1 voltage drops below 550m, V The peak inductor current at which the current comparator
corresponding to 0A. At this point switching cycles will be shuts off the top power switch is controlled by the voltage
skipped to keep the output voltage in regulation.
on the ITH pin.
Forced Continuous Mode Operation
In forced continuous mode the inductor current is con-
stantly cycled which creates a minimum output voltage
ripple at all output current levels.
Connecting the MODE/SYNC pin to ground will select the
forced continuous mode operation for VDDQ.
The forced continuous mode must be used if the output
is required to sink current.
If the output current increases, the error amplifier raises
the ITH pin voltage until the average inductor current
matches the new load current. In normal operation, the
LTC3618 clamps the maximum ITH pin voltage at ap-
proximately 1.05V which corresponds to about 5.5A peak
inductor current.
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. The
LTC3618 uses two techniques to prevent current runaway
from occurring:
Dropout Operation
1. If the output voltage drops below 50% of its nominal
As the input supply voltage approaches the output voltage,
the duty cycle increases toward the maximum on-time.
Further reduction of the supply voltage for ces the main
switch to remain on for more than one cycle, eventually
reaching 100% duty cycle. The output voltage will then be
determined by the input voltage minus the voltage drop
across the internal P-channel MOSFET and the inductor.
value, the clamp voltage at the ITH pin is lowered,
causing the maximum peak inductor current to lower
gradually with the output voltage. When the output volt-
age reaches 0V, the clamp voltage at the ITH pin drops
to 40% of the clamp voltage during normal operation.
The short-circuit peak inductor current is determined by
the minimum on-time of the TLC3618, the input voltage
and the inductor value. This foldback behavior helps
Low Supply Operation
in limiting the peak inductor current when the output
The LTC3618 is designed to operatdeown to aninputsupply
voltage of 2.25V. An important consideration at low input
supply voltages is that the RDS(ON) of the P-channel and
is shorted to ground. It is disabled during internal or
external soft-start and tracking up/down operation (see
the Applications Information section).
N-channel power switches increases by 50% compared to 2. If the inductor current of the bottom MOSFET increases
5V. The user should calculate the power dissipation when beyond 6A typical, the top power MOSFET will be held
the LTC3618 is used at 100% duty cycle with low input
off and switching cycles will be skipped until the induc-
voltages to ensure that thermal limits are not exceeded.
tor current reduces.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in current mode
constant-frequency architectures by preventing subhar -
monic oscillations at duty cycles greater than 50%. The
3618fb
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC3618.PDF ] | |
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