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PDF ATAES132 Data sheet ( Hoja de datos )
| Número de pieza | ATAES132 | |
| Descripción | 32K AES Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
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ATAES132
32K AES Serial EEPROM Specification
DATASHEET
Features
32Kb Standard Serial EEPROM User Memory
o Compatible with the Atmel® AT24C32D and the Atmel AT2530B
o 16 User Zones of 2Kb Each
High-security features
o AES Algorithm with 128-bit Keys
o AES-CCM for Authentication
o Message Authentication Code for Cryptographic Operations
o Secure Storage for Sixteen 128 bit Keys
o Encrypted User Memory Read and Write
o FIPS Random Number Generator
o 16 High-Endurance Monotonic EEPROM Counters
Flexible User Configured Security
o User Zone Access Rights Independently Configured
o Authentication Prior to Zone Access
Read/Write, Encrypted, or Read-only User Zone Options
High-speed Serial Interface Options
o 10MHz SPI (Mode 0 and 3)
o 1MHz I2C
2.5V to 5.5V Supply, <250nA Sleep
Serial EEPROM Compatible Pinout Packages: SOIC, SOP, or UDFN
Operating Temperature Range: -40°C to +85°C
Description
The Atmel ATAES132 is a high-security, Serial Electrically-Erasable and Programmable
Read-Only Memory (EEPROM) providing both authentication and confidential nonvolatile
data storage capabilities. Access restrictions for the 16 user zones are independently
configured and any key can be used with any zone. Keys can also be used for standalone
authentication. This flexibility permits the ATAES132 to be used in a wide range of
applications.
The AES-128 cryptographic engine operates in AES-CCM mode to provide authentication,
stored data encryption/decryption, and Message Authentication Codes. Data
encryption/decryption can be performed for internally stored data or for small external data
packets, depending upon the configuration. Data encrypted by one ATAES132 device can
be decrypted by another, and vice versa.
Atmel-8760C-CryptoAuth-ATAES132-Datasheet_102013
http://www.Datasheet4U.com
1 page  
I.8 AuthCheck Command – Counter MAC.................................................................................................................... 116
I.9 AuthCompute Command – Auth MAC..................................................................................................................... 116
I.10 AuthCompute Command – Counter MAC ............................................................................................................... 117
I.11 BlockRead Command.............................................................................................................................................. 117
I.12 Counter Command MAC ......................................................................................................................................... 117
I.13 Crunch Command ................................................................................................................................................... 118
I.14 DecRead Command................................................................................................................................................ 118
I.15 Decrypt Command MAC.......................................................................................................................................... 119
I.16 EncRead Command MAC ....................................................................................................................................... 120
I.17 EncRead Command Configuration Memory Signature MAC................................................................................... 120
I.18 EncRead Command Key Memory Signature MAC .................................................................................................. 121
I.19 Encrypt Command MAC.......................................................................................................................................... 122
I.20 EncWrite Command MAC ....................................................................................................................................... 122
I.21 INFO command ....................................................................................................................................................... 122
I.22 KeyCreate Command MAC ..................................................................................................................................... 123
I.23 KeyImport Command — KeyCreate MAC ............................................................................................................... 123
I.24 KeyLoad Command MAC........................................................................................................................................ 124
I.25 KeyTransfer Command ........................................................................................................................................... 124
I.26 Legacy Command ................................................................................................................................................... 124
I.27 Lock Command MAC .............................................................................................................................................. 124
I.28 Nonce Command .................................................................................................................................................... 125
I.29 NonceCompute Command ...................................................................................................................................... 125
I.30 Random Command ................................................................................................................................................. 125
I.31 Reset Command ..................................................................................................................................................... 125
I.32 Sleep Command...................................................................................................................................................... 125
I.33 WriteCompute Command ........................................................................................................................................ 126
Appendix J. I2C Interface .................................................................................................................................... 127
J.1 I2C Serial Interface Description................................................................................................................................ 127
J.2 Pin Descriptions ...................................................................................................................................................... 129
J.3 I2C Instruction Set.................................................................................................................................................... 130
J.4 I2C Interface Synchronization Procedure................................................................................................................. 134
J.5 I2C Auth Signaling ................................................................................................................................................... 134
J.6 I2C Compatibility ...................................................................................................................................................... 135
J.7 Timing Diagrams ..................................................................................................................................................... 136
Appendix K. SPI Interface.................................................................................................................................... 137
K.1 SPI Serial Interface Description............................................................................................................................... 137
K.2 SPI Communication Mode Pin Descriptions ............................................................................................................ 138
K.3 SPI Instruction Set................................................................................................................................................... 139
K.4 Timing Diagram ....................................................................................................................................................... 143
Appendix L. Power Management ........................................................................................................................ 144
L.1 Power State Descriptions ........................................................................................................................................ 144
L.2 Power State Transitions .......................................................................................................................................... 145
L.3 Understanding the ChipState Register .................................................................................................................... 148
Appendix M. Block Checksum.............................................................................................................................. 151
M.1 Checksum Function................................................................................................................................................. 152
M.2 Checksum Examples............................................................................................................................................... 152
Appendix N. ATAES132 Command Response Time........................................................................................... 153
Appendix O. Default Configuration ...................................................................................................................... 157
O.1 Configuration Memory Contents .............................................................................................................................. 158
O.2 Key Memory Contents ............................................................................................................................................. 160
ATAES132 [Datasheet]
Atmel-8760C-CryptoAuth-ATAES132-Datasheet_102013
5
5 Page 
2. Memory
The ATAES132 EEPROM is a nonvolatile memory which is divided into several sections with each section having
a different function. The User Memory section contains 32Kb for data storage. The Configuration Memory section
contains the configuration information, security control registers, and counters. The Key Memory stores the 16
secret keys used to perform cryptographic functions. The EEPROM page length is 32 bytes. The ATAES132
SRAM buffers and registers are located near the top of the memory address space and are accessed using
standard EEPROM Read/Write commands.
The complete memory map is shown in Appendix B, Memory Map. Each portion of the memory is described
briefly in the following sections.
2.1 User Memory
The 32Kb User Memory is organized as 16 user zones of 2Kb each. Each user zone has an associated user zone
configuration register in the Configuration Memory. A user zone can only be accessed when the security
requirements specified in the associated user zone configuration register have been satisfied. All bytes within a
user zone have the same access restrictions. Since the user zone access restrictions are independently
configured, the security requirements for each user zone can be unique. Any key can be used with any user zone.
Each user zone can be configured to require authentication, Read Encryption, Write Encryption, a combination of
these, or no security. The User Memory can be accessed directly with standard SPI or I2C commands if a user
zone is configured for open or read-only access. If the user zone security is activated, then the extended
ATAES132 command set is used to access the contents of a user zone.
2.1.1
Automatic Post Write Data Verification
The Write and EncWrite commands include an automatic data verification function. After the EEPROM Write is
complete, the Data Verification Logic reads the new EEPROM contents and compares it to the data received from
the Host. If the data does not match, the ATAES132 sets the EERR bit in the STATUS Register and returns a
DataMatch error code. If the data is correct, then the ReturnCode indicates success.
2.2 Key Memory
The Key Memory securely stores 16 keys which are each 128 bits long. Each key has an associated Key
Configuration Register in the Configuration Memory. Keys can only be used for the cryptographic functions
enabled in the Key Configuration Register. Individual keys can be configured to require a successful
authentication prior to use. Key values can never be read from the ATAES132 under any circumstances. See
Appendix F, Key Memory Map.
Key Memory can be written prior to locking with either encrypted or cleartext data. Encrypted writes are
performed using the EncWrite command (see Section 7.11, EncWrite Command). Cleartext writes are performed
using the standard SPI or I2C Write commands (see Section 5.2, Write). After locking, the Key Registers are
managed with the KeyCreate, KeyImport, KeyLoad, and KeyTransfer commands. The KeyTransfer command
allows the User Memory to be used as the Extended Key Memory; eight keys can be stored in each user zone
(see Section 7.16, KeyTransfer Command).
ATAES132 [Datasheet]
Atmel-8760C-CryptoAuth-ATAES132-Datasheet_102013
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