ADV7174 Datasheet PDF - Analog Devices
| Part Number | ADV7174 | |
| Description | Chip Scale PAL/NTSC Video Encoder | |
| Manufacturers | Analog Devices | |
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Data Sheet
Chip Scale PAL/NTSC Video Encoder with
Advanced Power Management
ADV7174/ADV7179
FEATURES
ITU-R1 BT601/BT656 YCrCb to PAL/NTSC video encoder
High quality 10-bit video DACs
SSAF™ (super sub-alias filter)
Advanced power management features
CGMS (copy generation management system)
WSS (wide screen signaling)
NTSC M, PAL N2, PAL B/D/G/H/I, PAL-M3 , PAL 60
Single 27 MHz clock required (×2 oversampling)
Macrovision 7.1 (ADV7174 only)
80 dB video SNR
32-bit direct digital synthesizer for color subcarrier
Multistandard video output support:
Composite (CVBS)
Component S-video (Y/C)
Video input data port supports:
CCIR-656 4:2:2 8-bit parallel input format
Programmable simultaneous composite and S-video or RGB
(SCART)/YPbPr video outputs
Programmable luma filters low-pass [PAL/NTSC] notch,
extended SSAF, CIF, and QCIF
Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,
1.2 MHz, and 2.0 MHz], CIF, and QCIF)
Programmable VBI (vertical blanking interval)
Programmable subcarrier frequency and phase
Programmable LUMA delay
Individual on/off control of each DAC
CCIR and square pixel operation
Integrated subcarrier locking to external video source
Color signal control/burst signal control
Interlaced/noninterlaced operation
Complete on-chip video timing generator
Programmable multimode master/slave operation
Closed captioning support
Teletext insertion port (PAL-WST)
On-board color bar generation
On-board voltage reference
2-wire serial MPU interface (I2C® compatible and fast I2C)
Single-supply 2.8 V and 3.3 V operation
Small 40-lead 6 mm × 6 mm LFCSP package
−40°C to +85°C at 3.3 V
−20°C to +85°C at 2.8 V
Qualified for automotive applications
APPLICATIONS
Portable video applications
Mobile phones
Digital still cameras
VAA
RESET
COLOR
DATA
P7–P0
FUNCTIONAL BLOCK DIAGRAM
TTXREQ TTX
POWER
MANAGEMENT
CONTROL
(SLEEP MODE)
ADV7174/ADV7179
CGMS AND WSS
INSERTION
BLOCK
TELETEXT
INSERTION
BLOCK
YUV TO
RBG
MATRIX
8
4:2:2 TO
4:4:4
INTER-
8
POLATOR
8
Y8
YCrCb
TO
YUV
U8
MATRIX
V8
ADD 9 INTER- 9
SYNC
POLATOR
8
ADD
BURST 8
8
INTER-
POLATOR 8
PROGRAMMABLE
LUMINANCE
FILTER
10
PROGRAMMABLE
CHROMINANCE
FILTER
10
10
U
V
10
10
M
U 10
L
T
I
P
10
10-BIT
DAC
10-BIT
L DAC
10
E
X
10
10-BIT
E DAC
R
DAC A (PIN 29)
DAC B (PIN 28)
DAC C (PIN 24)
HSYNC
FIELD/VSYNC
BLANK
VIDEO TIMING
GENERATOR
I2C MPU PORT
REAL-TIME
CONTROL
CIRCUIT
10 10
SIN/COS
DDS BLOCK
VOLTAGE
REFERENCE
CIRCUIT
VREF
RSET
COMP
CLOCK
SCLOCK SDATA ALSB
SCRESET/RTC
GND
Figure 1.
1 ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
2 Throughout the document, N is referenced to PAL – Combination – N.
3 ADV7174 only.
The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest
Macrovision version available.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
ADV7174/ADV7179
2.8 V TIMING SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX1, unless otherwise noted.
Table 2.
Parameter
MPU PORT2, 3
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 4
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT4, 5
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, tPD5
TELETEXT3, 4, 6
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
Conditions1
After this period the first clock is generated
Relevant for repeated start condition
Min Typ Max Unit
0 400 kHz
0.6 µs
1.3 µs
0.6 µs
0.6 µs
100 ns
300 ns
300 ns
0.6 µs
7 ns
0 ns
27
8
8
3.5
4
4
3
12
8
48
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
23 ns
2 ns
6 ns
6 ns
1 Temperature range TMIN to TMAX: –20°C to +85°C.
2 TTL input values are 0 V to 2.8 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
3 Guaranteed by characterization.
4 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
5 See Figure 60.
6 Teletext Port consists of the following:
Teletext Output: TTXREQ
Teletext Input: TTX
Rev. C | Page 5 of 52
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| Information | Total 30 Pages | |
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| Download | [ ADV7174.PDF Datasheet ] | |
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