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ON Semiconductor - CAT28C512

Numéro de référence 28C512
Description CAT28C512
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28C512 fiche technique
CAT28C512/513
512K-Bit CMOS PARALLEL EEPROM
FEATURES
s Fast Read Access Times: 120/150 ns
s Low Power CMOS Dissipation:
–Active: 50 mA Max.
–Standby: 200 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–5ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel EEPROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
BLOCK DIAGRAM
s Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC and TSOP packages.
A7A15
VCC
CE
OE
WE
A0A6
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
65,536 x 8
EEPROM
ARRAY
128 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0I/O7
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1007, Rev. I

PagesPages 12
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