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PDF HD1-6408-9 Data sheet ( Hoja de datos )
| Número de pieza | HD1-6408-9 | |
| Descripción | CMOS Asynchronous Serial Manchester Adapter (ASMA) | |
| Fabricantes | Intersil Corporation | |
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HD-6408
March 1997
CMOS Asynchronous Serial
Manchester Adapter (ASMA)
Features
Description
• Low Bit Error Rate
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encoder, Decoder
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
• Single Power Supply
• 24 Lead Package
Ordering Information
PACKAGE
PDIP
CERDIP
TEMP. RANGE
-40oC to +85oC
-40oC to +85oC
PART
NUMBER
HD3-6408-9
HD1-6408-9
PKG.
NO.
E24.6
E24.6
The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder
for creating a very high speed asynchronous serial data bus.
The Encoder converts serial NRZ data (typically from a shift
register) to Manchester II encoded data, adding a sync pulse
and parity bit. The Decoder recognizes this sync pulse and
identifies it as a Command Sync or a Data Sync. The data is
then decoded and shifted out in NRZ code (typically into a
shift register). Finally, the parity bit is checked. If there were
no Manchester or parity errors the Decoder responds with a
valid word signal. The Decoder puts the Manchester code to
full use to provide clock recovery and excellent noise immu-
nity at these very high speeds.
The HD-6408 can be used in many commercial applications
such as security systems, environmental control systems,
serial data links and many others. It utilizes a single 12 x
clock and achieves data rates of up to one million bits per
second with a very minimum overhead of only 4 bits out of
20, leaving 16 bits for data.
Pinout
d
HD-6408 (DIP)
TOP VIEW
VW 1
ESC 2
TD 3
SDO 4
DC 5
BZI 6
BOI 7
UDI 8
DSC 9
CDS 10
DR 11
GND 12
24 VCC
23 EC
22 SCI
21 SD
20 SS
19 EE
18 SDI
17 BOO
16 OI
15 BZO
14 DBS
13 MR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-1
File Number 2952.1
1 page  
HD-6408
Decoder Operation
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DClock input. The
Manchester II coded data can be presented to the Decoder
in one of two ways. The BOI and BZI inputs will accept data
from a differential output comparator. The UDI input can only
accept noninverted Manchester II coded data (e.g. from
BOO of an Encoder through an inverter to UDI).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized (1), the type of sync is indicated by the
CDS output. If the sync character was a command, this out-
put will go high (2) and remain high for sixteen DSC periods
(3), otherwise it will remain low. The TD output will go high
and remain high (2) - (3) while the Decoder is transmitting
the decoded data through SDO.
The decoded data available at SDO is in a NRZ format. The
DSC is provided so that the decoded bits can be shifted into
an external register on every low-to-high transition of this
clock (2) - (3). Note that DECODER SHIFT CLOCK may
adjust its phase up until the time that TAKE DATA goes high.
After all sixteen decoded bits have been transmitted (3) the
data is checked for odd parity. A high on VW output (4) indi-
cates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is look-
ing for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown (1).
At any time in the above sequence a high input on DR during
a low-to-high transition of DSC will abort transmission and ini-
tialize the Decoder to start looking for a new sync character.
TIMING
DSC
BOI
BZI
TD
CDS
SDO
VW
01234 5 678
1ST HALF 2ND HALF 15 14 13 12 11 10
SYNC SYNC 15 14 13 12 11 10
UNDEFINED
FROM PREVIOUS RECEPTION
15 14 13 12
12
16 17 18 19
2 1 0P
2 1 0P
43 210
34
5-5
5 Page 
Decoder Timing (Continued)
HD-6408
DSC
CDS
TD
DSC
SDO
DSC
CDS
TD
VW
DSC
DR
(31)
TD6
TD6
(32)
(33)
TD8
(34)
TD8
(35)
TD10
DATA BIT
(34) TD11
(34) TD11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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