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PDF ATmega164A Data sheet ( Hoja de datos )
| Número de pieza | ATmega164A | |
| Descripción | 8-bit Atmel Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
8-bit Atmel Microcontroller with 16/32/64/128K Bytes
In-System Programmable Flash
DATASHEET
Features
High-performance, low-power 8-bit Atmel® AVR® Microcontroller
Advanced RISC architecture
̶ 131 powerful Instructions – most single-clock cycle execution
̶ 32 × 8 general purpose working registers
̶ Fully static operation
̶ Up to 20MIPS throughput at 20MHz
̶ On-chip 2-cycle multiplier
High endurance non-volatile memory segments
̶ 16/32/64/128KBytes of In-System Self-programmable Flash program memory
̶ 512/1K/2K/4KBytes EEPROM
̶ 1/2/4/16KBytes Internal SRAM
̶ Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
̶ Data retention: 20 years at 85°C/ 100 years at 25°C(1)
̶ Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
̶ Programming Lock for Software Security
Atmel QTouch® library support
̶ Capacitive touch buttons, sliders and wheels
̶ QTouch and QMatrix acquisition
̶ Up to 64 sense channels
JTAG (IEEE std. 1149.1 Compliant) Interface
̶ Boundary-scan Capabilities According to the JTAG Standard
̶ Extensive On-chip Debug Support
̶ Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
Interface
Peripheral Features
̶ Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
̶ One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
̶ Real Time Counter with Separate Oscillator
̶ Six PWM Channels
̶ 8-channel, 10-bit ADC
Differential mode with selectable gain at 1×, 10× or 200×
̶ Byte-oriented Two-wire Serial Interface
̶ Two Programmable Serial USART
̶ Master/Slave SPI Serial Interface
Atmel-8272G-AVR-01/2015
1 page  
1.3 Pinout - VFBGA for Atmel ATmega164A/164PA/324A/324PA
Figure 1-3. VFBGA - pinout.
Top view
1234567
A
B
C
D
E
F
G
Bottom view
7654321
A
B
C
D
E
F
G
Table 1-2.
A
B
C
D
E
F
G
BGA - pinout.
12
GND
PB4
PB6 PB5
VCC
RESET
GND
XTAL2
XTAL1
PD1
PD2 PD3
GND
PD4
3
PB2
PB3
PB7
PD0
PD5
PD6
VCC
4
GND
PB0
PB1
GND
PD7
PC0
GND
5
VCC
PA0
PA1
PA4
PC5
PC2
PC1
67
PA2 GND
PA3 PA5
PA6 AREF
PA7 GND
PC7 AVCC
PC4 PC6
PC3 GND
2. Overview
The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit
microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single
clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs
approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing
speed.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET]
Atmel-8272G-AVR-01/2015
5
5 Page 
operands are output from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing
– enabling efficient address calculations. One of the these address pointers can also be used as an address
pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-
register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register.
Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is
updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that
writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The
Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the
total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine
(before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space.
The data SRAM can easily be accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit
in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts
have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the
higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the
Register File, 0x20 - 0x5F. In addition, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has
Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can
be used.
7.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and
an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and
bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
7.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction.
This information can be used for altering program flow in order to perform conditional operations. Note that the
Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in
many cases remove the need for using the dedicated compare instructions, resulting in faster and more
compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET]
Atmel-8272G-AVR-01/2015
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATmega164A.PDF ] | |
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