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PDF ADG1407 Data sheet ( Hoja de datos )
| Número de pieza | ADG1407 | |
| Descripción | CMOS Multiplexers | |
| Fabricantes | Analog Devices | |
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Data Sheet
9.5 Ω RON, 16-Channel, Differential 8-Channel,
±15 V/+12 V/±5 V iCMOS Multiplexers
ADG1406/ADG1407
FEATURES
9.5 Ω on resistance at 25°C
Up to 300 mA of continuous current
Fully specified at ±15 V/+12 V/±5 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Medical equipment
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
FUNCTIONAL BLOCK DIAGRAMS
ADG1406
S1
D
S16
1-OF-16
DECODER
A0 A1 A2 A3 EN
Figure 1.
ADG1407
S1A
DA
S8A
GENERAL DESCRIPTION
The ADG1406 and ADG1407 are monolithic iCMOS® analog
multiplexers comprising 16 single channels and eight differential
channels, respectively. The ADG1406 switches one of 16 inputs
to a common output, as determined by the 4-bit binary address
lines (A0, A1, A2, and A3). The ADG1407 switches one of eight
differential inputs to a common differential output, as determined
by the 3-bit binary address lines (A0, A1, and A2). An EN input
on both devices enables or disables the device. When disabled,
all channels switch off. When on, each channel conducts equally
well in both directions and has an input signal range that extends
to the supplies.
The industrial CMOS (iCMOS) modular manufacturing
process combines high voltage complementary metal-oxide
semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
S1B
S8B
1-OF-8
DECODER
DB
A0 A1 A2 EN
Figure 2.
of high voltage devices has been able to achieve. Unlike analog
ICs using conventional CMOS processes, iCMOS components
can tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications where low distortion is critical. iCMOS
construction ensures ultralow power dissipation, making the
devices ideally suited for portable and battery-powered instruments.
Table 1. Related Devices
Device No.
Description
ADG1206/ADG1207 Low capacitance, low charge injection,
and low leakage 8-/16-channel ±15 V
multiplexers
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADG1406/ADG1407
Parameter
tON (EN)
tOFF (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG1406
ADG1407
Insertion Loss
CS (Off )
CD (Off )
ADG1406
ADG1407
CD, CS (On)
ADG1406
ADG1407
POWER REQUIREMENTS
IDD
IDD
VDD
+25°C
145
205
112
150
10
−73
−70
35
70
0.6
12
145
72
166
93
0.002
150
−40°C to +85°C
250
175
−40°C to +125°C1
285
200
1
475
5/16.5
Unit
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
MHz typ
MHz typ
dB typ
pF typ
pF typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 31
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 35
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 36
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
1 Temperature range for B version: −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. C | Page 5 of 20
5 Page 
Data Sheet
ADG1406/ADG1407
VDD 1
DB 2
NC 3
S8B 4
S7B 5
S6B 6
S5B 7
S4B 8
S3B 9
S2B 10
S1B 11
GND 12
NC 13
NC 14
ADG1407
TOP VIEW
(Not to Scale)
28 DA
27 VSS
26 S8A
25 S7A
24 S6A
23 S5A
22 S4A
21 S3A
20 S2A
19 S1A
18 EN
17 A0
16 A1
15 A2
S8B 1
S7B 2
S6B 3
S5B 4
S4B 5
S3B 6
S2B 7
S1B 8
ADG1407
TOP VIEW
(Not to Scale)
24 S8A
23 S7A
22 S6A
21 S5A
20 S4A
19 S3A
18 S2A
17 S1A
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE TIED TO
THE SUBSTRATE, VSS.
NC = NO CONNECT
Figure 5. ADG1407 TSSOP Pin Configuration
Figure 6. ADG1407 LFCSP Pin Configuration
Table 11. ADG1407 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic Description
1 29 VDD Most Positive Power Supply Potential.
2 31 DB Drain Terminal B. This pin can be an input or an output.
3, 13, 14
11, 12, 13, 26, NC
28, 30, 32
No Connect.
4 1 S8B Source Terminal 8B. This pin can be an input or an output.
5 2 S7B Source Terminal 7B. This pin can be an input or an output.
6 3 S6B Source Terminal 6B. This pin can be an input or an output.
7 4 S5B Source Terminal 5B. This pin can be an input or an output.
8 5 S4B Source Terminal 4B. This pin can be an input or an output.
9 6 S3B Source Terminal 3B. This pin can be an input or an output.
10 7
S2B Source Terminal 2B. This pin can be an input or an output.
11 8
S1B Source Terminal 1B. This pin can be an input or an output.
12 9
GND Ground (0 V) Reference.
15 10 A2 Logic Control Input.
16 14 A1 Logic Control Input.
17 15 A0 Logic Control Input.
18 16 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19 17 S1A Source Terminal 1A. This pin can be an input or an output.
20 18 S2A Source Terminal 2A. This pin can be an input or an output.
21 19 S3A Source Terminal 3A. This pin can be an input or an output.
22 20 S4A Source Terminal 4A. This pin can be an input or an output.
23 21 S5A Source Terminal 5A. This pin can be an input or an output.
24 22 S6A Source Terminal 6A. This pin can be an input or an output.
25 23 S7A Source Terminal 7A. This pin can be an input or an output.
26 24 S8A Source Terminal 8A. This pin can be an input or an output.
27 25 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
28 27 DA Drain Terminal A. This pin can be an input or an output.
Not applicable 0
EPAD
Exposed Pad. The exposed pad must be tied to the substrate, VSS.
Rev. C | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADG1407.PDF ] | |
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