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PDF 18F45K80 Data sheet ( Hoja de datos )
| Número de pieza | 18F45K80 | |
| Descripción | PIC18F45K80 | |
| Fabricantes | Microchip | |
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PIC18FXXK80 FAMILY
Flash Microcontroller Programming Specification
1.0 DEVICE OVERVIEW
This document includes the programming specifications
for the following devices:
• PIC18F25K80
• PIC18LF25K80
• PIC18F45K80
• PIC18LF45K80
• PIC18F65K80
• PIC18LF65K80
• PIC18F26K80
• PIC18LF26K80
• PIC18F46K80
• PIC18LF46K80
• PIC18F66K80
• PIC18LF66K80
2.0 PROGRAMMING OVERVIEW
The PIC18FXXK80 family of devices can be
programmed using the In-Circuit Serial Programming™
(ICSP™) method. This programming specification
applies to the PIC18FXXK80 family of devices in all
package types.
2.1 Hardware Requirements
When programming with the ICSP, the PIC18FXXK80
family requires two programmable power supplies; one
for VDD and one for MCLR/VPP/RE3. Both supplies
should have a minimum resolution of 0.25V. Refer to
Section 6.0 “AC/DC Characteristics Timing
Requirements for Program/Verify Test Mode” for
additional hardware parameters.
2.1.1
LOW-VOLTAGE ICSP™
PROGRAMMING
In Low-Voltage ICSP mode, the PIC18FXXK80 family
can be programmed using a VDD source in the operat-
ing range. The MCLR/VPP/RE3 pin does not have to be
brought to a different voltage, but can instead, be left at
the normal operating voltage. Refer to Section 6.0
“AC/DC Characteristics Timing Requirements for
Program/Verify Test Mode” for additional hardware
parameters.
2.2 Pin Diagrams
The pin diagrams for the PIC18FXXK80 family are
shown in Figure 2-1 and Figure 2-2.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXXK80 FAMILY
Pin Name
Pin Name
Pin Type
During Programming
Pin Description
MCLR/VPP/RE3
VDD(1)
VSS(1)
VPP
VDD
VSS
P Programming Enable
P Power Supply
P Ground
AVDD
AVDD
P Analog Power Supply
AVSS
AVSS
P Analog Ground
RB6
PGC
I Serial Clock
RB7
PGD
I/O Serial Data
VDDCORE/
VCAP
VDDCORE
VCAP
P Regulated Power Supply for Microcontroller Core
I Filter Capacitor for On-Chip Voltage Regulator
Legend: I = Input, O = Output, P = Power
Note 1: All power supply (VDD) and ground (VSS) pins must be connected.
2011 Microchip Technology Inc.
DS39972B-page 1
Free Datasheet http://www.Datasheet-PDF.com/
1 page  
PIC18FXXK80 FAMILY
FIGURE 2-4:
PIC18F8XKXX FAMILY PIN DIAGRAMS
44-PIN TQFP/QFN
The following devices are included in 44-pin TQFP/QFN parts:
• PIC18F45K80
• PIC18F46K80
• PIC18LF45K80
• PIC18LF46K80
RC7 1
RD4 2
RD5 3
RD6 4
RD7 5
VSS
VDD
6
7
RB0 8
RB1 9
RB2 10
RB3 11
PIC18F4XK80
33 N/C
32 RC0
31 RA6
30 RA7
29 VSS
28 VDD
27 RE2
26 RE1
25 RE0
24 RA5
23 VDDCORE/VCAP
2011 Microchip Technology Inc.
DS39972B-page 5
Free Datasheet http://www.Datasheet-PDF.com/
5 Page 
PIC18FXXK80 FAMILY
2.5 High-Level Overview of the
Programming Process
Figure 2-9 shows the high-level overview of the
programming process. First, a Block Erase is performed
for each block. Next, the code memory, ID locations and
data EEPROM are programmed. These memories are
then verified to ensure that programming was successful.
If no errors are detected, the Configuration bits are then
programmed and verified.
FIGURE 2-9:
HIGH-LEVEL
PROGRAMMING FLOW
Start
Perform Sequential
Block Erase
Procedure
Program Memory
Program IDs
Program Data EE
Verify Program
2.6 Entering and Exiting High-Voltage
ICSP Program/Verify Mode
As shown in Figure 2-11, entering High-Voltage ICSP
Program/Verify mode requires two steps. First, voltage
is applied to the MCLR pin. Second, a 32-bit key
sequence is presented on PGD.
The programming voltage applied to MCLR is VIHH.
VIHH must be applied to MCLR during the transfer of
the key sequence. After VIHH is applied to MCLR, an
interval of at least P12 must elapse before presenting
the key sequence on PGD.
The key sequence is a specific 32-bit pattern,‘0100
1101 0100 0011 0100 1000 0101 0000’ (more
easily remembered as 4D434850h in hexadecimal).
The device will enter Program/Verify mode only if the
sequence is valid. The Most Significant bit of the most
significant nibble must be shifted in first.
Once the key sequence is complete, Program/Verify
mode is entered, and the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
Exiting Program/Verify mode is done by removing VIHH
from MCLR, as shown in Figure 2-13. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and the program signals on
PGC and PGD before removing VIHH.
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
2011 Microchip Technology Inc.
DS39972B-page 11
Free Datasheet http://www.Datasheet-PDF.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 18F45K80.PDF ] | |
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