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PDF SPCA536A Data sheet ( Hoja de datos )
| Número de pieza | SPCA536A | |
| Descripción | Advanced Imaging Controller | |
| Fabricantes | Sunplus | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SPCA536A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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MAR. 23, 2004
Version 1.0
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
1 page  
SPCA536A
3.ARCHITECTURE BLOCK DIAGRAM
The heart of SPCA536A is a powerful 32-bit RISC CPU and a rich
set of hardware engines. All the engines can work simultaneously
to achieve the highest performance. The interfaces to external
components are flexible enough, allowing SPCA536A to work with
a variety of sensors, LCD panels and storage media.
SDRAM
up to 512M
l LYCMOS/
CCD
tia Nsensors
sensor
interface
controller
Color
DSP
DRAM interfcae
DRAM
controller
DMA controller
USB2.0
controller
USB 1.1
USB host
USB
PC
onfidenUSE O4channels
ADC
RTC
PLL
Global
control
Clock
generat
or
Display
interface
controller
MJPEG
engine
Video
triple-DAC
plus CPLUShardwaredirectlink
CPU bus
STN/TFT
LCD
panel
TV
Audio
controller
CPU bridge
Audi
o
code
c
32-bit RISC
Instruction cache
Data cache
Instruction RAM
Data RAM
external
Mic
audio
codec
speaker
Storage media interface
controller
external
ROM
NAND/
SD/
MMC/
CFC/
SMC/
MS
external
peripherals
Sun RLDSensor interface controller The sensor interface controller
Ogenerates the timing required by the CMOS sensors or CCD
sensors. SPCA536A supports dual sensor inputs. It also embeds a
Wserial interface to control the CMOS sensors or the CDS/AGC
chips.
ForPLL SPCA536’s requires only an external crystal. All the required
CPU can be disabled and release the control to an external CPU.
The CPU handles audio compression and decompression. It can
also perform image post-processing. The CPU integrates 2K-byte
instruction cache, 2K-byte data cache, 2K-byte instruction RAM
and 8K-byte data RAM. The instruction RAM allows the CPU to
execute the firmware with the cache-access speed without slowing
down by the cache-miss. The data RAM allows the CPU to access
clocks are generated by the on-chip PLL. If the application
data without cache-miss, too. The SPCA536A’s DMA controller
supports composite TV output, the frequency of the crystal must
can swap data between external SDRAM and the data RAM at the
be 27MHz. Otherwise, 6MHz, 12MHz, 24MHz, 48MHz are all
extremely high speed. SPCA536A can process the image either
applicable. SPCA536A uses IO-trap for crystal frequency
by a build-in ColorDSP, by the RISC CPU or combination of both.
selection.
Color DSP Image processing engine of the SPCA536.
Global control and clock generator These module controls the
reset sequence, suspend/resume and clock frequency
DRAM controller The DRAM controller provides access path to
adjustments. It also performs power management by turning off
the SDRAM for the other internal modules of the SPCA536.
the unused clock.
SPCA536A supports SDRAM. The DRAM controller also
integrates acceleration engines for a variety of graphic function,
CPU The 32-bit RISC CPU coordinates the camera operation. The
such as image scaling, rotation, mirror, BitBlit,…etc. Depending on
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
5
MAR. 23, 2004
Version: 1.0
5 Page 
SPCA536A
Pin No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
Pin Name
Dir.
Description
Memo
rgb1
I Sensor data1
horizontal valid
rgb2
I Sensor data2
Data0
rgb3
I Sensor data3
Data1
rgb4
I Sensor data4
Data2
rgb5
I Sensor data5
Data3
rgb6
I Sensor data6
Data4
rgb7
rgb8
Yrgb9
tial LTggpio0
NTggpio1
n OTggpio2
eTggpio3
fid ETggpio4
Tggpio5
STggpio6
on UTggpio7
Tggpio8
C STggpio9
s UTggpio10
lu LTggpio11
Tggpio12
p PTggpio13
un LDXtali
S RXtalo
xtalrtci
Oxtalrtco
suspend
Wtrap
rprstnn
Fotestmode
I Sensor data7
Data5
I Sensor data8
Data6
I Sensor data9
Data7
Single sensor
Dual sensor
B Tggpio0 S2_exthd
B Tggpio1 S2_extvd
B Tggpio2
S2_adck
B Tggpio3
S2_sen
B Tggpio4
S2_sck
B Tggpio5
S2_sdo
B Tggpio6
S2_rgb0
B Tggpio7
S2_rgb1
B Tggpio8
S2_rgb2
B Tggpio9
S2_rgb3
B Tggpio10
S2_rgb4
B Tggpio11
S2_rgb5
B Tggpio12
S2_rgb6
B Tggpio13
S2_rgb7
Global Control Pins
I Crystal pad input (6MHz/12MHz/24MHz/27MHz/48MHz). Default 27MHz
O Crystal pad output
I 32768Hz crystal pad input
O 32768Hz crystal pad output
O USB suspend signal
O IO-trap control signal.
I Power-on reset to SPCA536
I Test mode. This pin must be at low state during normal operation.
ADC Interface
CHD
I For flash-light cut-off
CHC
I For UI interface
CHB
I For battery power detection
AGCOUT
O
1st stage Amplifier Output
ADCVREF
O
ADC voltage reference. It must connect to ground via a 0.1uF capacitor.
OPO
O 2nd stage Amplifier output
OPI I 2nd stage Amplifier input
AGC
I AGC Gain Control
MICN
I Micro-phone input-
MICP
I Micro-phone input+
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
11
MAR. 23, 2004
Version: 1.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SPCA536A.PDF ] | |
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