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Número de pieza | TM035NDH01 | |
Descripción | LCD Module | |
Fabricantes | TIANMA | |
Logotipo | ||
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Coversheet
TM035NDH01 V1.1
MODEL NO. :
ISSUED DATE:
VERSION :
TM035NDH01
2010-07-27
Ver 1.1
■Preliminary Specification
□Final Product Specification
Customer :
Approved by
Notes
SHANGHAI TIANMA Confirmed :
Prepared by
Checked by
Approved by
This technical specification is subjected to change without notice
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 1 of 21
1 page SHANGHAI TIANMA MICRO-ELECTRONICS
2. Input/Output Terminals
TM035NDH01 V1.1
2.1 CN1 pin assignment of FPC
Connector type: FH12-40S-0.5S (HRS)
No Symbol
I/O
Description
Comment
1 IM0
I Select the MPU interface mode
Note 1
2 IM1
I Select the MPU interface mode
Note 1
3 IM2
I Select the MPU interface mode
Note 1
4 DB17
I/O Data Bus
Note 2
5 DB16
I/O Data Bus
Note 2
6 DB15
I/O Data Bus
Note 2
7 DB14
I/O Data Bus
Note 2
8 DB13
I/O Data Bus
Note 2
9 DB12
I/O Data Bus
Note 2
10 DB11
I/O Data Bus
Note 2
11 DB10
I/O Data Bus
Note 2
12 DB9
I/O Data Bus
Note 2
13 DB8
I/O Data Bus
Note 2
14 GND
I/O Ground
Note 2
15 DB7
I/O Data Bus
Note 2
16 DB6
I/O Data Bus
Note 2
17 DB5
I/O Data Bus
Note 2
18 DB4
I/O Data Bus
Note 2
19 DB3
I/O Data Bus
Note 2
20 DB2
I/O Data Bus
Note 2
21 DB1
I/O Data Bus
Note 2
22 DB0
I/O Data Bus
Note 2
23 GND
P Ground
24 RD
I Read control pin for the CPU interface Note 2
25 WR
I Write control pin for the CPU interface Note 2
or SPI clock
26 RS
I Display data or Command selection Note 2
27 CS
I Chip select
Note 2
28 IOVCC
P Power supply for interface pins
29 VCI
P Power supply for analog circuit
30 GND
P Ground
31 RESET
I IC reset
32 DCLK
I Dot clock signal for RGB interface
operation
33 GND
P Ground
34 DE
I Data enable signal
35 HSYNC
I Horizontal synchronizing signal
36 VSYNC
I Vertical synchronizing signal
37 DIN
I Serial data input
Note 2
38 DOUT
O Serial data output
Note 2
39 LED+
P LED anode
40 LED-
P LED cathode
I/O definition:
I----Input O----Output P----Power/Ground
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 5 of 21
5 Page SHANGHAI TIANMA MICRO-ELECTRONICS
TM035NDH01 V1.1
5.2 SPI Interface Timing
(VCI=2.6V~3.0V, IOVCC=2.6V~3.0V,GND=0V, Ta=25℃)
Signal
Symbol
Parameter
Min Max Unit
CS
tcss Chip Select setup time(Write)
tcsh Chip Select hold time(Write)
40 -
40 -
ns
ns
tas Address setup time
10
RS
tah Address hold time(Write/Read)
10
ns
ns
WR
(Write)
twc Write cycle
twrh SCL High duration(Write)
twrl SCL Low duration(Write)
100
40
40
ns
ns
ns
WR
(Read)
trc Read cycle
trdh SCL High duration(Read)
trdl SCL Low duration(Read)
300
120
120
ns
ns
ns
DIN
(Driver IC)
tds Data setup time
tdh Data hold time
30 ns
30 ns
DOUT
(Driver IC)
tacc Access time
-
tod Output disable time
10
Table 5.2 SPI Interface Timing
110
ns
ns
Figure 5.2 SPI Interface Timing
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 11 of 21
11 Page |
Páginas | Total 21 Páginas | |
PDF Descargar | [ Datasheet TM035NDH01.PDF ] |
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