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PDF CS5523 Data sheet ( Hoja de datos )
| Número de pieza | CS5523 | |
| Descripción | 2/4/8-channel ADCs | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5521/22/23/24/28
16-bit or 24-bit, 2/4/8-channel ADCs with PGIA
Features
Low Input Current (100 pA), Chopper-
stabilized Instrumentation Amplifier
Scalable Input Span (Bipolar/Unipolar)
- 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V,
2.5 V, 5 V
- External: 10 V, 100 V
Wide VREF Input Range (+1 to +5 V)
Fourth Order Delta-Sigma A/D Converter
Easy to Use Three-wire Serial Interface Port
- Programmable/Auto Channel Sequencer with
Conversion Data FIFO
- Accessible Calibration Registers per Channel
- Compatible with SPI™ and Microwire™
System and Self Calibration
Eight Selectable Word Rates
- Up to 617 Sps (XIN = 200 kHz)
- Single Conversion Settling
- 50/60 Hz ±3 Hz Simultaneous Rejection
Single +5 V Power Supply Operation
- Charge Pump Drive for Negative Supply
- +3 to +5 V Digital Supply Operation
Low Power Consumption: 6.0 mW
General Description
The CS5521/22/23/24/28 are highly integrated ΔΣ ana-
log-to-digital converters (ADCs) which use charge-
balance techniques to achieve 16-bit (CS5521/23) and
24-bit (CS5522/24/28) performance. The ADCs come as
either two-channel (CS5521/22), four-channel
(CS5523/24), or eight-channel (CS5528) devices and
include a low-input-current, chopper-stabilized instru-
mentation amplifier. To permit selectable input spans of
25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs
include a PGA (programmable gain amplifier). To ac-
commodate ground-based thermocouple applications,
the devices include a charge pump drive which provides
a negative bias voltage to the on-chip amplifiers.
These devices also include a fourth-order ΔΣ modulator
followed by a digital filter which provides eight selectable
output word rates. The digital filters are designed to settle
to full accuracy within one conversion cycle and when
operated at word rates below 30 Sps, they reject both
50 Hz and 60 Hz interference.
These single-supply products are ideal solutions for
measuring isolated and non-isolated, low-level signals in
process control applications.
ORDERING INFORMATION
See page 53.
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
NBV
MUX
CS5524
Shown
VA+ AGND VREF+ VREF-
DGND VD+
X1
+
X20
X1
X1
Differential
4th Order
ΔΣ
Modulator
Digital Filter
Controller,
Setup Registers,
&
Channel Scan
Logic
Latch
Clock
Gen.
Data FIFO &
Calibration Registers
Serial Port
Interface
CPD
A0 A1 XIN XOUT
CS
SCLK
SDI
SDO
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009
(All Rights Reserved)
JUL ‘09
DS317F8
1 page  
CS5521/22/23/24/28
CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25° C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND,
NBV = -2.1 V, XIN = 32.768 kHz, CFS1-CFS0 = ‘00’, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input
Range = ±100 mV; See Notes 1 and 2.)
Parameter
Accuracy
Resolution
Linearity Error
Bipolar Offset
(Note 3)
Unipolar Offset
(Note 3)
Offset Drift
(Notes 3 and 4)
Bipolar Gain Error
Unipolar Gain Error
Gain Drift
(Note 4)
Power Supplies
Power Supply Currents (Normal Mode)
IA+
(Note 5)ID+
INBV
Power Consumption
(Note 6)
Normal Mode
Low Power Mode
Sleep
Power Supply Rejection
Positive Supplies
dc NBV
CS5521/23
Min Typ Max
- - 16
- ±0.0015 ±0.003
- ±1 ±2
- ±2 ±4
- 20 -
- ±8 ±31
- ±16 ±62
- 13
- 1.2 1.6
- 110 150
- 400 570
- 7.0 10
N/A N/A N/A
- 500 -
- 120 -
- 110 -
CS5522/24/28
Min Typ Max
Unit
- - 24 Bits
- ±0.0007 ±0.0015 %FS
- ±16 ±32 LSBN
- ±32 ±64 LSBN
- 20 - nV/°C
- ±8 ±31 ppm
- ±16 ±62 ppm
- 1 3 ppm/°C
- 1.5 2.1 mA
- 110 150 µA
- 525 700 µA
- 10.1 14.8 mW
- 5.5 7.5 mW
- 500 - µW
- 120 - dB
- 110 - dB
Notes: 1. Applies after system calibration at any temperature within -40° C ~ +85° C.
2. Specifications guaranteed by design, characterization, and/or test.
3. Specification applies to the device only and does not include any effects by external parasitic
thermocouples. LSBN: N is 16 for the CS5521/23 and N is 24 for the CS5522/24/28
4. Drift over specified temperature range after calibration at power-up at 25° C.
5. Measured with Charge Pump Drive off.
6. All outputs unloaded. All input CMOS levels and the CS5521/23 do not have a low power mode.
DS317F8
5
5 Page 
CS5521/22/23/24/28
SWITCHING CHARACTERISTICS (TA = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;
Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF.))
Parameter
Master Clock Frequency
(Note 25)
External Clock or Internal Oscillator (CS5522/24/28)
(CS5521/23)
Master Clock Duty Cycle
Symbol
XIN
Min Typ Max Unit
30 32.768 200 kHz
30 32.768 130 kHz
40 - 60 %
Rise Times
(Note 26)
Any Digital Input Except SCLK
SCLK
Any Digital Output
trise
- - 1.0 µs
- - 100 µs
- 50 - ns
Fall Times
(Note 26)
Any Digital Input Except SCLK
SCLK
Any Digital Output
tfall
- - 1.0 µs
- - 100 µs
- 50 - ns
Start-up
Oscillator Start-up Time
Serial Port Timing
XTAL = 32.768 kHz (Note 27)
tost
- 500 - ms
Serial Clock Frequency
SCLK
0
-
2 MHz
SCLK Falling to CS Falling for continuous running SCLK
(Note 28)
Serial Clock
Pulse Width High
Pulse Width Low
SDI Write Timing
t0
t1
t2
100 -
250 -
250 -
- ns
- ns
- ns
CS Enable to Valid Latch Clock
Data Set-up Time prior to SCLK rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
SDO Read Timing
t3 50 -
t4 50 -
t5 100 -
t6 100 -
- ns
- ns
- ns
- ns
CS to Data Valid
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
t7 - - 150 ns
t8 - - 150 ns
t9 - - 150 ns
Notes: 25. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 200 kHz
(CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput.
26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
28. Applicable when SCLK is continuously running.
Specifications are subject to change without notice.
DS317F8
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5523.PDF ] | |
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