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PDF MX25L8036E Data sheet ( Hoja de datos )
| Número de pieza | MX25L8036E | |
| Descripción | 8M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX25L8036E
MX25L8036E
DATASHEET
P/N: PM1571
REV. 1.0, MAR. 30, 2010
1
1 page  
MX25L8036E
8M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 8M:8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/O
read mode) structure
• 256 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 16 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 133MHz with 8 dummy cycles
- 2 I/O: 108MHz with 4 dummy cycles for 2READ instruction; 133MHz with 8 dummy cycles for DREAD
instruction
- 4 I/O: 133MHz with 6 dummy cycles
- Fast access time: 133MHz serial clock
- Serial clock of two I/O read mode : 108MHz (2READ); 133MHz (DREAD)
- Serial clock of four I/O read mode : 133MHz, which is equivalent to 532MHz
- Fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.4s(typ.) /block (64K-byte per block); 3s(typ.) /chip
• Low Power Consumption
- Low active read current: 35mA(max.) at 133MHz, and 10mA(max.) at 50MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (typ.) ; 50uA (max.)
- Deep power-down current: 3uA (typ.) ; 20uA (max.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase
instructions
- Additional 4K-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
P/N: PM1571
REV. 1.0, MAR. 30, 2010
5
5 Page 
MX25L8036E
Table 2. Protected Area Sizes
Status bit
BP3 BP2 BP1
000
000
001
001
010
010
011
011
100
100
101
101
110
110
111
111
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Level
8Mb
0 (none)
1 (1block, 1/16 area, block#15)
2 (2blocks, 1/8 area, block#14-15)
3 (4blocks, 1/4 area, block#12-15)
4 (8blocks, 1/2 area, block#8-15)
5 (16blocks, all)
6 (16blocks, all)
7 (16blocks, all)
8 (16blocks, all)
9 (16blocks, all)
10 (16blocks, all)
11 (8blocks, 1/2 area, block#0-7)
12 (12blocks, 3/4 area, block#0-11)
13 (14blocks, 7/8 area, block#0-13)
14 (15block, 15/16 area, block#0-14)
15 (16blocks, all)
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de-
vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-
cured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu-
rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-
cured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxx1FF
Size
128-bit
3968-bit
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
Determined by customer
P/N: PM1571
REV. 1.0, MAR. 30, 2010
11
11 Page | ||
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