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PDF MX29F1615 Data sheet ( Hoja de datos )
| Número de pieza | MX29F1615 | |
| Descripción | 16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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FEATURES
• 5V ± 10% write and erase
• JEDEC-standard EEPROM commands
• Endurance:100 cycles
• Fast access time: 90/100/120ns
• Auto Erase and Auto Program Algorithms
- Automatically erases the whole chip
- Automatically programs and verifies data at
specified addresses
• Status Register feature for detection of
program or erase cycle completion
• Low VCC write inhibit is equal to or less than 3.2V
PRELIMINARY
MX29F1615
16M-BIT [2M x8/1M x16] CMOS
SINGLE VOLTAGE FLASH EEPROM
• Software and hardware data protection
• Page program operation
- Internal address and data latches for 64 words per
page
- Page programming time: 0.9ms typical
• Low power dissipation
- 30mA typical active current
- 1uA typical standby current
• CMOS and TTL compatible inputs and outputs
• Package Type:
- 42 lead PDIP
GENERAL DESCRIPTION
The MX29F1615 is a 16-mega bit Flash memory organized
as either 1M wordx16 or 2M bytex8. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memory. The
MX29F1615 is packaged in 42-pin PDIP. It is designed
to be reprogrammed and in standard EPROM
programmers.
The standard MX29F1615 offers access times as fast as
90ns,allowing operation of high-speed microprocessors
without wait. To eliminate bus contention, the MX29F1615
has separate chip enables(CE) and output enable (OE)
control.
MXIC's Flash memories augment EPROM functionality
with electrical erasure and programming. The MX29F1615
uses a command register to manage this functionality.
The command register allows for 100% TTL level control
inputs and fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
To allow for simple in-system reprogrammability, the
MX29F1615 requires high input voltages (10V) on BYTE/
VPP pin for programming. Reading data out of the device
is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 100 cycles. The MXIC's cell is designed to
optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29F1615 uses a 5V ± 10% VCC supply to perform the
Auto Erase and Auto Program algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
P/N: PM0615
1 REV.1.1, JUN. 15, 2001
1 page  
MX29F1615
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
Table2.1 Bus Operations
Mode
Notes CE OE BYTE/VPP A0 A1 A9 Q0-Q7 Q8-Q14
Q15/A-1
Read
1,5 VIL VIL
VIH/VIL
X X X DOUT HighZ/DOUT VIL/VIH/DOUT
Output Disable
1 VIL VIH
VIH/VIL
X
X
X
High Z
HIghZ
HighZ/X
Standby
1 VIH
X
X
XXX
X
X
X
Manufacturer ID 2,4 VIL VIL
VIH/VIL
VIL VIL VID
C2H High Z/00H
VIL/OB
Device ID
MX29F1615
2,4 VIL VIL
VIH/VIL
VIH VIL VID
6BH High Z/00H
VIL/OB
Write
1,3,6 VIL VIH
VHH
XXX
DIN
DIN
DIN
NOTES :
1. X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes.
3. Commands for different Erase operations or Data program operations can only be successfully completed through proper command
sequence.
4. VID = 11.5V- 12.5V.
5. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.
6.VHH=9.5V~10.5V
P/N: PM0615
REV. 1.1, JUN. 15, 2001
5
5 Page 
DATA PROTECTION
The MX29F1615 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read Array mode.
Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up and
power-down, a write cycle is locked out for VCC less than
VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the
command register is disabled and all internal program/
erase circuits are disabled. Under this condition the device
will reset to the read mode. Subsequent writes will be
ignored until the VCC level is greater than VLKO. It is the
user's responsibility to ensure that the control pins are
logically correct to prevent unintentional write when VCC is
above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE will not
initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE =
VIH or BYTE/VPP=VIH/VIL To initiate a write cycle CE
must be a logical zero, BYTE/VPP must be at VHH while
OE is a logical one.
MX29F1615
P/N: PM0615
REV. 1.1, JUN. 15, 2001
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MX29F1615.PDF ] | |
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