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PDF MX29LV161DB Data sheet ( Hoja de datos )
| Número de pieza | MX29LV161DB | |
| Descripción | FLASH MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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ADVANCED INFORMATION
MX29LV161D T/B
16M-BIT [1M x 16] 3V SUPPLY FLASH MEMORY
MX29LV161D T/B
DATASHEET
P/N:PM1359
REV. 0.09, JUL. 29, 2008
1
1 page  
ADVANCED INFORMATION
MX29LV161D T/B
16M-BIT [1M x 16] 3V SUPPLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Word mode only
- 1,048,576 x 16
• Sector Structure
- 8K-Word x 1, 4K-Word x 2, 16K-Word x 1, 32K-Word x 31
- Provides sector protect function to prevent program or erase operation in the protected sector
- Provides chip unprotect function to allow code changing
- Provides temporary sector unprotect function for code changing in previously protected sector
• Power Supply Operation
- Vcc 2.7 to 3.6 volt for read, erase, and program operations
- VI/O 1.65V to 3.6V for Input/Output
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc <= Vlko
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Fast access time: 90ns
- Word program time: 11us/word (typical)
- Fast erase time: 0.7s/sector, 15s/chip (typical)
• Low Power Consumption
- Low active read current: 5mA (typical) at 5MHz
- Low standby current: 5uA (typical)
• 100,000 erase/program cycle (typical)
• 10 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC
- Provide accelerated program capability
PACKAGE
• 48-Pin TSOP
• 48-Ball CSP (TFBGA)
• 48-Ball WFBGA/XFLGA
• All Pb-free devices are RoHS Compliant
P/N:PM1359
REV. 0.09, JUL. 29, 2008
5
5 Page 
ADVANCED INFORMATION
MX29LV161D T/B
BLOCK DIAGRAM DESCRIPTION
The block diagram on Page 10 illustrates a simplified architecture of MX29LV161D T/B. Each block in the block
diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the memory
array.
The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET# and WP#/ACC. It creates
internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER" to
latch the external address pins A0-AM(A19). The internal addresses are output from this block to the main array and
decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", and "FLASH ARRAY". The X-DECODER
decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines of the flash array. The bit lines
are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through the y-pass gates.
Sense amplifiers are used to read out the contents of the flash memory, while the "PGM DATA HV" block is used to
selectively deliver high power to bit-lines during programming.The "I/O BUFFER" controls the input and output on the
Q0-Q15 pads. During read operation, the I/O buffer receives data from sense amplifiers and drives the output pads
accordingly. In the last cycle of program command, the I/O buffer transmits the data on Q0-Q15 to "PROGRAM DATA
LATCH", which controls the high power drivers in "PGM DATA HV" to selectively program the bits in a word according
to the user input pattern.
The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary high
voltage to the "X-DECODER", "FLASH ARRAY", and "PGM DATA HV" block. The logic control module comprises of
the "WRITE STATE MACHINE(WSM)", "STATE REGISTER", "COMMAND DATA DECODER", and "COMMAND DATA
LATCH".When the user issues a command by toggling WE#, the command on Q0-Q15 is latched in the command data
latch and is decoded by the command data decoder.The state register receives the command and records the current
state of the device. The WSM implements the internal algorithms for program or erase according to the current com-
mand state by controlling each block in the block diagram.
P/N:PM1359
REV. 0.09, JUL. 29, 2008
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX29LV161DB.PDF ] | |
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