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PDF MT29F32G08AFACA Data sheet ( Hoja de datos )
| Número de pieza | MT29F32G08AFACA | |
| Descripción | NAND Flash Memory | |
| Fabricantes | Micron | |
| Logotipo |  |
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Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F16G08ABACA, MT29F32G08AFACA
MT29F16G08ABCCB, MT29F32G08AECCB, MT29F64G08AKCCB
Features
• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Block size: 128 pages (512K + 28K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 16Gb: 4096 blocks;
32Gb: 8192 blocks; 64Gb: 16,384 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 5
– Clock rate: 10ns (DDR)
– Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
– tRC/tWC: 20ns (MIN)
• Array performance
– Read page: 35µs (MAX)
– Program page: 350µs (TYP)
– Erase block: 1.5ms (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 1.7-1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 100).
• RESET (FFh) required as first command after pow-
er-on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: JESD47 compliant; see qualifica-
tion report
– Endurance: 60,000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 48-pin TSOP
– 100-ball BGA
Note: 1. The ONFI 2.2 specification is available at
www.onfi.org.
PDF: 09005aef844588dc
M72A_16Gb_32Gb_64Gb_AsyncSync_NAND.pdf – Rev. G 5/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb Asynchronous/Synchronous NAND
Features
List of Figures
Figure 1: Part Numbering ................................................................................................................................ 2
Figure 2: 48-Pin TSOP Type 1 (Top View) ........................................................................................................ 11
Figure 3: 100-Ball BGA (Ball-Down, Top View) ................................................................................................ 12
Figure 4: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................. 13
Figure 5: 100-Ball VBGA – 12mm x 18mm (Package Code: H1) ......................................................................... 14
Figure 6: 100-Ball TBGA – 12mm x 18mm (Package Code: H2) ......................................................................... 15
Figure 7: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 16
Figure 8: Device Organization for Single-Die Package (TSOP/BGA) ................................................................. 17
Figure 9: Device Organization for Two-Die Package (TSOP) ............................................................................. 18
Figure 10: Device Organization for Two-Die Package (BGA) ............................................................................. 19
Figure 11: Device Organization for Four-Die Package (BGA) ............................................................................ 20
Figure 12: Array Organization per Logical Unit (LUN) ..................................................................................... 21
Figure 13: Asynchronous Command Latch Cycle ............................................................................................ 23
Figure 14: Asynchronous Address Latch Cycle ................................................................................................ 24
Figure 15: Asynchronous Data Input Cycles .................................................................................................... 25
Figure 16: Asynchronous Data Output Cycles ................................................................................................. 26
Figure 17: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 27
Figure 18: READ/BUSY# Open Drain .............................................................................................................. 28
Figure 19: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 29
Figure 20: tFall and tRise (VCCQ = 1.7-1.95V) .................................................................................................... 29
Figure 21: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 30
Figure 22: IOL vs Rp (VCCQ = 1.7-1.95V) .......................................................................................................... 30
Figure 23: TC vs Rp ........................................................................................................................................ 31
Figure 24: Synchronous Bus Idle/Driving Behavior ......................................................................................... 34
Figure 25: Synchronous Command Cycle ....................................................................................................... 35
Figure 26: Synchronous Address Cycle ........................................................................................................... 36
Figure 27: Synchronous DDR Data Input Cycles ............................................................................................. 37
Figure 28: Synchronous DDR Data Output Cycles ........................................................................................... 39
Figure 29: R/B# Power-On Behavior ............................................................................................................... 40
Figure 30: Activating the Synchronous Interface ............................................................................................. 43
Figure 31: RESET (FFh) Operation .................................................................................................................. 46
Figure 32: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 47
Figure 33: RESET LUN (FAh) Operation .......................................................................................................... 48
Figure 34: READ ID (90h) with 00h Address Operation .................................................................................... 49
Figure 35: READ ID (90h) with 20h Address Operation .................................................................................... 49
Figure 36: READ PARAMETER (ECh) Operation .............................................................................................. 51
Figure 37: READ UNIQUE ID (EDh) Operation ............................................................................................... 58
Figure 38: SET FEATURES (EFh) Operation .................................................................................................... 60
Figure 39: GET FEATURES (EEh) Operation .................................................................................................... 60
Figure 40: READ STATUS (70h) Operation ...................................................................................................... 66
Figure 41: READ STATUS ENHANCED (78h) Operation ................................................................................... 66
Figure 42: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 67
Figure 43: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation .......................................................... 68
Figure 44: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 69
Figure 45: CHANGE ROW ADDRESS (85h) Operation ...................................................................................... 71
Figure 46: READ PAGE (00h-30h) Operation ................................................................................................... 75
Figure 47: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 76
Figure 48: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 78
Figure 49: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 79
Figure 50: READ PAGE MULTI-PLANE (00h-32h) Operation ............................................................................ 81
PDF: 09005aef844588dc
M72A_16Gb_32Gb_64Gb_AsyncSync_NAND.pdf – Rev. G 5/12 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
5 Page 
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb Asynchronous/Synchronous NAND
Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync Async
x8 x8
Async
x8
Sync
x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
W/R#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
CLK
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
DNU/VSSQ2 DNU/VSSQ2
NC NC
46 NC
NC
45 NC
NC
44 DQ7 DQ7
43 DQ6 DQ6
42 DQ5 DQ5
41 DQ4 DQ4
40 NC
NC
39 DNU/VCCQ2 DNU/VCCQ2
38 DNU DNU
37 VCC
VCC
36 VSS
VSS
35 DNU DQS
34
33
DNU/VCCQ2 DNU/VCCQ2
NC NC
32 DQ3 DQ3
31 DQ2 DQ2
30 DQ1 DQ1
29 DQ0 DQ0
28 NC
NC
27 NC
NC
26 DNU DNU
25 DNU/VSSQ2 DNU/VSSQ2
Notes:
1. CE2# and R/B2# are available on dual die packages. They are NC for other configura-
tions.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.2. If not supplying VCCQ or
VSSQ to these pins, do not use them.
3. TSOP devices do not support the synchronous interface.
PDF: 09005aef844588dc
M72A_16Gb_32Gb_64Gb_AsyncSync_NAND.pdf – Rev. G 5/12 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
11 Page | ||
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