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PDF MT29F64G08CBCAB Data sheet ( Hoja de datos )
| Número de pieza | MT29F64G08CBCAB | |
| Descripción | NAND Flash Memory | |
| Fabricantes | Micron | |
| Logotipo |  |
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Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F64G08CBAA[A/B], MT29F128G08C[E/F]AAA, MT29F128G08CFAAB,
MT29F256G08C[J/K/M]AAA, MT29F256G08CJAAB, MT29F512G08CUAAA,
MT29F64G08CBCAB, MT29F128G08CECAB, MT29F256G08C[K/M]CAB,
MT29F512G08CUCAB
Features
• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Multiple-level cell (MLC) technology
• Organization
– Page size x8: 8640 bytes (8192 + 448 bytes)
– Block size: 256 pages (2048K + 112K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 64Gb: 4096 blocks;
128Gb: 8192 blocks;
256Gb: 16,384 blocks;
512Gb: 32,786 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 52
– Clock rate: 10ns (DDR)
– Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
– tRC/tWC: 20ns (MIN)
– Up to asynchronous timing mode 5
– Read/write throughput per pin: 50 MT/s
• Array performance
– Read page: 75µs (MAX)
– Program page: 1300µs (TYP)
– Erase block: 3.8ms (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 109).
• RESET (FFh) required as first command after power-
on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: JESD47G compliant; see qualifica-
tion report
– Endurance: 3000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 52-pad LGA
– 48-pin TSOP
– 100-ball BGA
Notes:
1. The ONFI 2.2 specification is available at
www.onfi.org.
2. BGA devices up to Synchronous timing
mode 5. TSOP devices up to Synchronous tim-
ing mode 4.
PDF: 09005aef83d2277a
Rev. E 3/11 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Features
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 26
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 27
Table 4: Synchronous Interface Mode Selection ............................................................................................. 37
Table 5: Command Set .................................................................................................................................. 48
Table 6: Read ID Parameters for Address 00h ................................................................................................. 54
Table 7: Read ID Parameters for Address 20h .................................................................................................. 54
Table 8: Parameter Page Data Structure ......................................................................................................... 56
Table 9: Feature Address Definitions .............................................................................................................. 68
Table 10: Feature Address 01h: Timing Mode ................................................................................................. 70
Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 71
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 71
Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 72
Table 14: Status Register Definition ............................................................................................................... 73
Table 15: OTP Area Details ........................................................................................................................... 104
Table 16: Error Management Details ............................................................................................................. 109
Table 17: Shared Pages ................................................................................................................................. 110
Table 18: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 112
Table 19: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 112
Table 20: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 113
Table 21: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 113
Table 22: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 114
Table 23: Overshoot/Undershoot Parameters ................................................................................................ 115
Table 24: Test Conditions for Input Slew Rate ................................................................................................ 116
Table 25: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 116
Table 26: Input Slew Rate (VCCQ= 2.7–3.6V) ................................................................................................... 116
Table 27: Test Conditions for Output Slew Rate ............................................................................................. 117
Table 28: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 117
Table 29: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 117
Table 30: Absolute Maximum Ratings by Device ............................................................................................ 118
Table 31: Recommended Operating Conditions ............................................................................................ 118
Table 32: Valid Blocks per LUN ..................................................................................................................... 118
Table 33: Capacitance: 100-Ball BGA Package ................................................................................................ 119
Table 34: Capacitance: 48-Pin TSOP Package ................................................................................................ 119
Table 35: Capacitance: 52-Pad LGA Package .................................................................................................. 119
Table 36: Test Conditions ............................................................................................................................. 120
Table 37: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 120
Table 38: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 121
Table 39: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 121
Table 40: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 122
Table 41: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 122
Table 42: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 124
Table 43: Array Characteristics ..................................................................................................................... 127
PDF: 09005aef83d2277a
Rev. E 3/11 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
5 Page 
Micron Confidential and Proprietary
64Gb, 128Gb, 256Gb, 512Gb Asynchronous/Synchronous NAND
Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync Async
x8 x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
W/R#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
CLK
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Async
x8
Sync
x8
48
47
DNU/VSSQ2 DNU/VSSQ2
NC NC
46 NC
NC
45 NC
NC
44 DQ7 DQ7
43 DQ6 DQ6
42 DQ5 DQ5
41 DQ4 DQ4
40 NC
NC
39 DNU/VCCQ2 DNU/VCCQ2
38 DNU DNU
37 VCC
VCC
36 VSS
VSS
35 DNU DQS
34
33
DNU/VCCQ2 DNU/VCCQ2
NC NC
32 DQ3 DQ3
31 DQ2 DQ2
30 DQ1 DQ1
29 DQ0 DQ0
28 NC
NC
27 NC
NC
26 DNU DNU
25 DNU/VSSQ2 DNU/VSSQ2
Notes:
1. CE2# and R/B2# are available on dual die and quad die packages. They are NC for other
configurations.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.2. If not supplying VCCQ or
VSSQ to these pins, do not use them.
PDF: 09005aef83d2277a
Rev. E 3/11 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT29F64G08CBCAB.PDF ] | |
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