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PDF MT29F32G08CFACA Data sheet ( Hoja de datos )

Número de pieza MT29F32G08CFACA
Descripción NAND Flash Memory
Fabricantes Micron　
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Micron Confidential and Proprietary
16Gb, 32Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F16G08CBACA, MT29F32G08CFACA, MT29F16G08CBACB,
MT29F32G08CFACB
Features
• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Multiple-level cell (MLC) technology
• Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Block size: 256 pages (1024K + 56K bytes)
– Plane size: 2 planes x 1024 blocks per plane
– Device size: 16Gb: 2048 blocks;
32Gb: 4096 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 4
– Clock rate: 12ns (DDR)
– Read/write throughput per pin: 166 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
– Read/write throughput per pin: 50 MT/s
– tRC/tWC: 20ns (MIN)
• Array performance
– Read page: 75µs (MAX)
– Program page: 1300µs (TYP)
– Erase block: 3.8ms (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 97).
• RESET (FFh) required as first command after pow-
er-on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: JESD47G compliant; see qualifi-
cation report
– Endurance: 3000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 56-ball BGA
– 48-pin TSOP
Note: 1. The ONFI 2.2 specification is available at
www.onfi.org.
PDF: 09005aef841356b0
L72A_16Gb_32Gb_Async_Sync_NAND.pdf – Rev. E 9/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




MT29F32G08CFACA pdf
Micron Confidential and Proprietary
16Gb, 32Gb Asynchronous/Synchronous NAND
Features
List of Figures
Figure 1: Part Numbering ................................................................................................................................ 2
Figure 2: 48-Pin TSOP Type 1 (Top View) ........................................................................................................ 11
Figure 3: 56-Ball BGA (Ball-Down, Top View) .................................................................................................. 12
Figure 4: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................. 13
Figure 5: 56-Ball VFBGA – 9.5mm x 12.8mm (Package Code: H5) ..................................................................... 14
Figure 6: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 15
Figure 7: Device Organization for Single-Die Package (TSOP/BGA) ................................................................. 16
Figure 8: Device Organization for Two-Die Package (TSOP) ............................................................................. 17
Figure 9: Array Organization per Logical Unit (LUN) ....................................................................................... 18
Figure 10: Asynchronous Command Latch Cycle ............................................................................................ 20
Figure 11: Asynchronous Address Latch Cycle ................................................................................................ 21
Figure 12: Asynchronous Data Input Cycles .................................................................................................... 22
Figure 13: Asynchronous Data Output Cycles ................................................................................................. 23
Figure 14: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 24
Figure 15: READ/BUSY# Open Drain .............................................................................................................. 25
Figure 16: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 26
Figure 17: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 26
Figure 18: TC vs Rp ........................................................................................................................................ 27
Figure 19: Synchronous Bus Idle/Driving Behavior ......................................................................................... 30
Figure 20: Synchronous Command Cycle ....................................................................................................... 31
Figure 21: Synchronous Address Cycle ........................................................................................................... 32
Figure 22: Synchronous DDR Data Input Cycles ............................................................................................. 33
Figure 23: Synchronous DDR Data Output Cycles ........................................................................................... 35
Figure 24: R/B# Power-On Behavior ............................................................................................................... 36
Figure 25: Activating the Synchronous Interface ............................................................................................. 39
Figure 26: RESET (FFh) Operation .................................................................................................................. 42
Figure 27: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 43
Figure 28: RESET LUN (FAh) Operation .......................................................................................................... 44
Figure 29: READ ID (90h) with 00h Address Operation .................................................................................... 45
Figure 30: READ ID (90h) with 20h Address Operation .................................................................................... 45
Figure 31: READ PARAMETER (ECh) Operation .............................................................................................. 47
Figure 32: READ UNIQUE ID (EDh) Operation ............................................................................................... 55
Figure 33: SET FEATURES (EFh) Operation .................................................................................................... 57
Figure 34: GET FEATURES (EEh) Operation .................................................................................................... 57
Figure 35: READ STATUS (70h) Operation ...................................................................................................... 63
Figure 36: READ STATUS ENHANCED (78h) Operation ................................................................................... 63
Figure 37: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 64
Figure 38: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation .......................................................... 65
Figure 39: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 66
Figure 40: CHANGE ROW ADDRESS (85h) Operation ...................................................................................... 68
Figure 41: READ PAGE (00h-30h) Operation ................................................................................................... 72
Figure 42: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 73
Figure 43: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 75
Figure 44: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 76
Figure 45: READ PAGE MULTI-PLANE (00h-32h) Operation ............................................................................ 78
Figure 46: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 80
Figure 47: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 82
Figure 48: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 82
Figure 49: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation .................................................................... 84
Figure 50: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 85
PDF: 09005aef841356b0
L72A_16Gb_32Gb_Async_Sync_NAND.pdf – Rev. E 9/12 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.

5 Page





MT29F32G08CFACA arduino
Micron Confidential and Proprietary
16Gb, 32Gb Asynchronous/Synchronous NAND
Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Notes:
Sync Async
x8 x8
Async
x8
Sync
x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
W/R#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
CLK
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 DNU/VSSQ2 DNU/VSSQ2
47 DNU DNU
46 NC
NC
45 NC
NC
44 DQ7
DQ7
43 DQ6
DQ6
42 DQ5
DQ5
41 DQ4
DQ4
40 NC
NC
39
38
DNU/VCCQ2 DNU/VCCQ2
DNU
DNU
37 VCC
VCC
36 VSS
VSS
35 DNU DQS
34 DNU/VCCQ2 DNU/VCCQ2
33 NC
NC
32 DQ3
DQ3
31 DQ2
DQ2
30 DQ1
DQ1
29 DQ0
DQ0
28 NC
NC
27 NC
NC
26 NC
NC
25 DNU/VSSQ2 DNU/VSSQ2
1. CE2# and R/B2# are available on dual die packages. They are NC for other configura-
tions.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.2. If not supplying VCCQ or
VSSQ to these pins, do not use them.
PDF: 09005aef841356b0
L72A_16Gb_32Gb_Async_Sync_NAND.pdf – Rev. E 9/12 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.

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