PDF AS7C32098A Data sheet ( Hoja de datos )

Número de pieza	AS7C32098A
Descripción	3.3 V 128K x 16 CMOS SRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! February 2006 ® 3.3 V 128K × 16 CMOS SRAM AS7C32098A Features • Industrial and commercial temperature • Organization: 131,072 words × 16 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time • Low power consumption: ACTIVE - 650 mW /max @ 10 ns • Low power consumption: STANDBY Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 WE I/O buffer 1024 × 128 × 16 Array (2,097,152) Control circuit Column decoder VCC GND UB OE LB CE - 28.8 mW /max CMOS • Individual byte read/write controls • Easy memory expansion with CE, OE inputs • TTL- and CMOS-compatible, three-state I/O • 44-pin JEDEC standard packages - TSOP 2 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Pin arrangement for TSOP 2 A0 1 44 A1 2 43 A2 3 42 A3 4 41 A4 5 40 CE 6 39 I/O1 7 38 I/O2 8 37 I/O3 9 36 I/O4 10 35 VCC 11 34 GND 12 33 I/O5 13 32 I/O6 14 31 I/O7 15 30 I/O8 16 29 WE 17 28 A5 18 27 A6 19 26 A7 20 25 A8 21 24 A9 22 23 A16 A15 A14 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VCC I/O12 I/O11 I/O10 I/O9 NC A13 A12 A11 A10 NC Selection guide Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current –10 –12 –15 –20 Unit 10 12 15 20 ns 4 5 6 7 ns Industrial 180 160 140 110 mA Commercial 170 150 130 100 mA 8 8 8 8 mA 2/17/06, v 1.1 Alliance Semiconductor P. 1 of 10 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C32098A ® Read waveform 2 (CE, OE, UB, LB controlled)5,7,8 tRC Address OE tOLZ tAA tOE CE tACE tCLZ LB, UB DataOUT tBLZ tBA tOHZ tOH Data valid tCHZ tBHZ Write cycle (over the operating range)9 –10 Parameter Symbol Min Max Write cycle time tWC 10 – Chip enable (CE) to write end tCW 7 – Address setup to write end tAW 7 – Address setup time tAS 0 – Write pulse width (OE = High) tWP1 7 – Write pulse width (OE = Low) tWP2 10 – Write recovery time tWR 0 – Address hold from end of write tAH 0 – Data valid to write end tDW 5 – Data hold time tDH 0 – Write enable to output in High-Z tWZ 0 5 Output active from write end tOW 3 – Byte enable Low to write end tBW 7 – –12 Min Max 12 – 8– 8– 0– 8– 12 – 0– 0– 6 0– 06 3– 8– –15 Min Max 15 – 10 – 10 – 0– 10 – 15 – 0– 0– 7– 0– 07 3– 10 – –20 Min Max 20 – 12 – 12 – 0– 12 – 20 – 0– 0– 9– 0– 09 3– 12 – Unit Note ns ns ns ns ns ns ns ns ns ns 3,4 ns 3,4 ns 3,4 ns 3,4 2/17/06, v 1.1 Alliance Semiconductor P. 5 of 10 5 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AS7C32098A	3.3 V 128K x 16 CMOS SRAM	Alliance Semiconductor
AS7C32098A-10TC	3.3 V 128K x 16 CMOS SRAM	Alliance Semiconductor
AS7C32098A-10TI	3.3 V 128K x 16 CMOS SRAM	Alliance Semiconductor
AS7C32098A-12TC	3.3 V 128K x 16 CMOS SRAM	Alliance Semiconductor

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