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AS7C32098A-12TC fiches techniques PDF

Alliance Semiconductor - 3.3 V 128K x 16 CMOS SRAM

Numéro de référence AS7C32098A-12TC
Description 3.3 V 128K x 16 CMOS SRAM
Fabricant Alliance Semiconductor 
Logo Alliance Semiconductor 





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AS7C32098A-12TC fiche technique
February 2006
®
3.3 V 128K × 16 CMOS SRAM
AS7C32098A
Features
• Industrial and commercial temperature
• Organization: 131,072 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
• Low power consumption: STANDBY
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
I/O
buffer
1024 × 128 × 16
Array
(2,097,152)
Control circuit
Column decoder
VCC
GND
UB
OE
LB
CE
- 28.8 mW /max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- TSOP 2
• ESD protection 2000 volts
• Latch-up current 200 mA
Pin arrangement for TSOP 2
A0 1
44
A1 2
43
A2 3
42
A3 4
41
A4 5
40
CE 6
39
I/O1 7
38
I/O2 8
37
I/O3 9
36
I/O4 10 35
VCC 11 34
GND 12 33
I/O5 13 32
I/O6 14 31
I/O7 15 30
I/O8 16 29
WE 17 28
A5 18 27
A6 19 26
A7 20 25
A8 21 24
A9 22 23
A16
A15
A14
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
A13
A12
A11
A10
NC
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
–10 –12 –15 –20 Unit
10 12 15 20 ns
4 5 6 7 ns
Industrial 180
160
140
110 mA
Commercial 170
150
130
100 mA
8 8 8 8 mA
2/17/06, v 1.1
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.

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