PDF AS7C34098A-12JC Data sheet ( Hoja de datos )

Número de pieza	AS7C34098A-12JC
Descripción	3.3 V 256 K x 16 CMOS SRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! August 2004 ® 3.3 V 256 K × 16 CMOS SRAM AS7C34098A Features • Pin compatible with AS7C34098 • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time • Low power consumption: ACTIVE - 650 mW /max @ 10 ns • Low power consumption: STANDBY - 28.8 mW /max CMOS • Individual byte read/write controls Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 WE bIu/Offer 1024 × 256 × 16 Array (4,194,304) Control circuit Column decoder VCC GND UB OE LB CE • Easy memory expansion with CE, OE inputs • TTL- and CMOS-compatible, three-state I/O • 44-pin JEDEC standard packages - 400-mil SOJ - TSOP 2 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Pin arrangement for SOJ and TSOP 2 44-pin (400 mil) SOJ TSOP2 A0 1 44 A1 2 43 A2 3 42 A3 4 41 A4 5 40 CE 6 39 I/O1 7 38 I/O2 8 37 I/O3 9 36 I/O4 10 35 GVNCDC 11 12 34 33 I/O5 I/O6 13 14 32 31 I/O7 15 30 I/O8 16 29 WE 17 28 A5 18 27 A6 19 26 A7 20 25 A8 21 24 A9 22 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VI/OCC12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 Selection guide Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current –10 –12 –15 –20 Unit 10 12 15 20 ns 45 6 7 ns Industrial 180 160 140 110 mA Commercial 170 150 130 100 mA 88 8 8 mA 8/17/04, v. 2.1 Alliance Memory Inc. P. 1 of 10 Copyright © Alliance Memory Inc. All rights reserved. 1 page AS7C34098A ® Read waveform 2 (CE, OE, UB, LB controlled)6,8,9 tRC Address OE tOLZ tAA tOE CE tACE tCLZ LB, UB DataOUT tBLZ tBA tOHZ tOH Data valid tCHZ tBHZ Write cycle (over the operating range)10 –10 Parameter Symbol Min Max Write cycle time tWC 10 – Chip enable (CE) to write end tCW 7 – Address setup to write end tAW 7 – Address setup time tAS 0 – Write pulse width (OE = High) tWP1 7 – Write pulse width (OE = Low) tWP2 10 – Write recovery time tWR 0 – Address hold from end of write tAH 0 – Data valid to write end tDW 5 – Data hold time tDH 0 – Write enable to output in High-Z tWZ 0 5 Output active from write end tOW 3 – Byte enable Low to write end tBW 7 – –12 Min Max 12 – 8– 8– 0– 8– 12 – 0– 0– 6 0– 06 3– 8– –15 Min Max 15 – 10 – 10 – 0– 10 – 15 – 0– 0– 7– 0– 07 3– 10 – –20 Min Max 20 – 12 – 12 – 0– 12 – 20 – 0– 0– 9– 0– 09 3– 12 – Unit Note ns ns ns ns ns ns ns ns ns ns 4, 5 ns 4, 5 ns 4, 5 ns 4, 5 8/17/04,v. 2.1 Alliance Memory Inc P. 5 of 10 5 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AS7C34098A-12JC	3.3 V 256 K x 16 CMOS SRAM	Alliance Semiconductor
AS7C34098A-12JI	3.3 V 256 K x 16 CMOS SRAM	Alliance Semiconductor

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