PDF AS7C34098A-8TIN Data sheet ( Hoja de datos )

Número de pieza	AS7C34098A-8TIN
Descripción	256K x 16 BIT HIGH SPEED CMOS SRAM
Fabricantes	Alliance Semiconductor
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No Preview Available !  Rev. 1.4 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue “CE# ≧VCC - 0.2V” revised as ”CE# ≦0.2V” for TEST CONDITION of Average Operating Power supply Current Icc1 on page3 Revised VIH(max)/VIL(min) in DC ELECTRICAL CHARACTERISTICS Added in tBA/tBHZ/tBLZ in AC ELECTRICAL CHARACTERISTICS Added WRITE CYCLE 3 in TIMING WAVEFORMS 1.Revise “TEST CONDITION” for VOH, VOL on page 5 IOH = -8mA revised as -4mA IOL =4mA revised as 8mA 2. Revise VIH(max) & VIL(min) note on page 5 VIH(max) = VCC + 2.0V for pulse width less than 6ns. VIL(min) = VSS - 2.0V for pulse width less than 6ns. Revised the address pin sequence of TSOP-II pin configuration on page 3 in order to be compatible with industry convention. (No function specifications and applications have been changed and all the characteristics are kept all the same as Rev 1.3 ) Added tBW in AC ELECTRICAL CHARACTERISTICS Revised WRITE CYCLE 1,2 in TIMING WAVEFORMS Issue Date Jul.12.2012 Jul.19.2012 May.7.2013 Jun.04.2013 Sep.23.2013 Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 0 1 page  Rev. 1.4 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 RATING -0.5 to 4.6 -0.5 to VCC+0.5 UNIT V V Operating Temperature TA -40 to 85(I grade) ℃ Storage Temperature TSTG -65 to 150 ℃ Power Dissipation PD 1 W DC Output Current IOUT 50 mA Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE CE# OE# WE# LB# Standby HX Output Disable LH LX LL Read LL LL LX Write LX LX Note: H = VIH, L = VIL, X = Don't care XX HX XH HL HH HL LL LH LL UB# X X H H L L H L L I/O OPERATION DQ0-DQ7 High – Z High – Z High – Z DOUT High – Z DOUT DIN High – Z DIN DQ8-DQ15 High – Z High – Z High – Z High – Z DOUT DOUT High – Z DIN DIN SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 4 5 Page  Rev. 1.4 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V IDR CE# ≧ VCC - 0.2V Others at 0.2V or Vcc – 0.2V tCDR See Data Retention Waveforms (below) tR DATA RETENTION WAVEFORM Vcc CE# Vcc(min.) tCDR VIH VDR ≥ 1.5V CE# ≥ Vcc-0.2V MIN. 1.5 - TYP. - 2 MAX. 3.6 10 UNIT V mA 0- tRC* - - ns - ns Vcc(min.) tR VIH Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 10 11 Page

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