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PDF AS8C403600 Data sheet ( Hoja de datos )
| Número de pieza | AS8C403600 | |
| Descripción | 3.3V Synchronous SRAMs | |
| Fabricantes | Alliance Semiconductor | |
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128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
AS8C403600
AS8C401800
Features
◆ 128K x 36, 256K x 18 memory configurations
◆ Supports high system speed:
Commercial:
– 150MHz 3.8ns clock access time
◆ LBO input selects interleaved or linear burst mode
◆ Self-timed write cycle with global write control ( Gl (W), byte
write enable (BWE), and byte writes (BWx)
◆ 3.3V core power supply
◆ Power down controlled by ZZ input
◆ 3.3V I/O
◆ Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆ Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP).
Pin Description Summary
A0-A17
Address In puts
CE Chip Enab le
CS0, CS1
Chip Se lects
OE Output Enable
GW Global Write Enable
BWE Byte Write Enable
BW1, BW2, BW3, BW4(1)
Individual By te Write Se lects
CLK Clock
ADV Burst Ad dress Advance
ADSC
Address Status (Cache Controller)
ADSP
Address S tatus (Processor)
LBO Linear / Interleaved Burst Order
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock
TDO Test Data Output
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Ou tput
VDD, VDDQ
Core P ower, I/O P ower
VSS Ground
NOTE:
1. BW3 and BW4 are not applicable for the AS8C401800.
Description
TheAS8C403600/1800 are high- speed SRAMs organized as
128K x 36/256K x 18. The AS8C403600/401800 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer,as theAS8C403600/1800 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (A( DV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The AS8C403600/1800 SRAMs utilize the latest high- performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
N/A
N/A
September 2010
1
DSC-5279/05
1 page  
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD / NC(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
,
5279 drw 02
TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to V DD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.542
5 Page 
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperat ure Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
,
61.412
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AS8C403600.PDF ] | |
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