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AS8C801801-QC150N fiches techniques PDF

Alliance Semiconductor - 3.3V Synchronous ZBT SRAMs

Numéro de référence AS8C801801-QC150N
Description 3.3V Synchronous ZBT SRAMs
Fabricant Alliance Semiconductor 
Logo Alliance Semiconductor 





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AS8C801801-QC150N fiche technique
256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
3.3V I/O, Burst Counter
Pipelined Outputs
AS8C803601
AS8C801801
Features
256K x 36, 512K x 18 memory configurations
Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (V DDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP).
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read or write.
TheAS8C803601/801801 contain data I/O, address and control signal
registers. Output enable is the only asynchronoussignal and can be
used to disable the outputsat any given time.
A Clock Enable(CEN) pin allows operation of the toAS8C803601/ 801801
be suspended as long as necessary. All synchronousinputs are ignored when
(CEN)is high and the internal device registers will hold their previous values.
There are three chip enable pins (CE1, CE2,CE2) that allow the user
to deselect the device when desired. If anyone of these three are not asserted
when ADV/LD is low, no new memoryoperation can be initiated. However,
any pending data transfers (reads or writes) will be completed. The data bus
will tri-state two cycles after chip is deselected or a write is initiated.
TheAS8C803601/801801 have an on-chip burst counter. In the burst
mode,the AS8C803601/801801 can provide fourcycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADVL/ D =LOW) or increment the internal burst counter
Description
The AS8C803601/801801 are3.3V high-speed 9,437,184 bit
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
(ADV/LD = HIGH).
The AS8C803601/801801 SRAM utilize IDT's latest high-performance
CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP) .
reads. Thus, they have been given the name ZBTMT, or Zero Bus Turnaround.
Pin Description Summary
A0-A18
Address Inputs
CE1, CE2, CE2
OE
R/W
Chip Enables
Output Enable
Read/Write S ignal
CEN Clock Enable
BW1, BW2, BW3, BW4
Individual Byte Write Selects
CLK
ADV/LD
Clock
Advance burst address / Load new address
LBO Linear / In terleaved B urst Order
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core P ower, I/ O Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Asynchronous
Synchronous
Static
Static
5304 tbl 01
SEPTEMBER 2010
1
DSC-5304/07

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