PDF AS7C4096A-20TC Data sheet ( Hoja de datos )

Número de pieza	AS7C4096A-20TC
Descripción	5.0V 512K x 8 CMOS SRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! February 2006 AS7C4096A ® 5.0V 512K × 8 CMOS SRAM Features • Pin compatible to AS7C4096 • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 5/6 ns output enable access time • Low power consumption: ACTIVE - 880mW/max @ 10 ns • Low power consumption: STANDBY - 55mW/max CMOS • Equal access and cycle times • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Logic block diagram VCC GND AA01 A2 A3 A4 A5 A6 A7 A8 A9 Input buffer 524,288 × 8 Array (4,194,304) Column decoder Control Circuit I/O1 I/O8 WE OE CE Pin arrangements 36-pin SOJ (400 mil) A0 A1 A2 A3 A4 CE I/O1 IG/VONC2DC I/O3 I/O4 WE A5 A6 A7 A8 A9 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 NC A18 A17 A16 A15 OE I/O8 I/O7 GVI/ONCC6D I/O5 A14 A13 A12 A11 A10 NC 44-pin TSOP 2 NC NC A0 A1 A2 1 2 3 54 44 43 42 4401 A3 A4 CE I/O1 IG/VONC2DC 6 7 8 9 10 11 12 39 38 37 36 35 34 33 I/O3 13 32 I/WO4E 14 31 15 30 AA56 16 29 17 28 A7 A8 AN9C 18 19 20 21 27 26 25 24 NC 22 23 NC NC AN1C8 A17 A16 A15 IO/OE8 I/O7 GVI/OCNC6D AI/O145 A13 A12 A11 NAC10 NC NC Selection guide Maximum address access time Maximum outputenable access time Maximum operating current Maximum CMOS standby current –10 –12 10 12 56 160 140 10 10 –15 15 6 120 10 –20 Unit 20 ns 6 ns 100 mA 10 mA 2/21/06, v 1.2 Alliance Semiconductor P. 1 of 10 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C4096A ® Write cycle (over the operating range)9 –10 Parameter Symbol Min Max Write cycle time tWC 10 – Chip enable (CE) to write end tCW 7 – Address setup to write end tAW 7 – Address setup time tAS 0 – Write pulse width (OE = high) tWP1 7 – Write pulse width (OE = low tWP2 10 – Address hold from end of write tAH 0 – Write recovery time tWR 0 – Data valid to write end tDW 5 – Data hold time tDH 0 – Write enable to output in high Z tWZ 2 5 Output active from write end tOW 3 – –12 Min Max 12 – 8– 8– 0– 8– 12 – 0– 0– 6– 0– 26 3– –15 Min Max 15 – 10 – 10 – 0– 10 – 15 – 0– 0– 7– 0– 27 3– –20 Min Max 20 – 12 – 12 – 0– 12 – 20 – 0– 0– 9– 0– 29 3– Unit Notes ns ns ns ns ns ns ns ns ns ns 3,4 ns 3,4 ns 3,4 Write waveform 1 (WE controlled)9 tWC Address WE DIN DOUT tAW tWP tAS tWZ tWR tAH tDW Data valid tDH tOW 2/21/06, v 1.2 Alliance Semiconductor P. 5 of 10 5 Page

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Número de pieza	Descripción	Fabricantes
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