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AS7C1026B-15TI fiches techniques PDF

Alliance Semiconductor - 5V 64K x 16 CMOS SRAM

Numéro de référence AS7C1026B-15TI
Description 5V 64K x 16 CMOS SRAM
Fabricant Alliance Semiconductor 
Logo Alliance Semiconductor 





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AS7C1026B-15TI fiche technique
March 2004
AS7C1026B
®
5 V 64K X 16 CMOS SRAM
Features
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS I/O
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
Logic block diagram
A0
A1
A2
A3
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
I/O
buffer
64 K × 16
Array
VCC
GND
Control circuit
WE Column decoder
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
• ESD protection 2000 volts
• Latch-up current 200 mA
Pin arrangement
44-Pin SOJ (400 mil), TSOP 2
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 GND
33 VCC
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
UB
OE
LB
CE
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
-10 -12 -15 -20 Unit
10 12 15 20 ns
5 6 7 8 ns
110 100
90
80 mA
10 10 10 10 mA
3/26/04, v 1.3
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.

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