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PDF AS7C4098-12JI Data sheet ( Hoja de datos )
| Número de pieza | AS7C4098-12JI | |
| Descripción | 5V/3.3V 256K x 16 CMOS SRAM | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AS7C4098-12JI (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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March 2002
®
5V/3.3V 256K × 16 CMOS SRAM
AS7C4098
AS7C34098
Features
• AS7C4098 (5V version)
• AS7C34098 (3.3V version)
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/max @ 12 ns
- 468 mW (AS7C34098)/max @ 12 ns
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
I/O
buffer
1024 × 256 × 16
Array
(4,194,304)
Control circuit
Column decoder
VCC
GND
UB
OE
LB
CE
• Low power consumption: STANDBY
- 110 mW (AS7C4098)/max CMOS
- 72 mW (AS7C34098)/max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
- 48-ball FBGA 7 x 11 mm
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
IV/COC12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
–10 –12 –15 –20 Unit
10 12 15 20 ns
56
7 9 ns
AS7C4098
–
250 220 180 mA
AS7C34098 160
130
110
100 mA
AS7C4098
–
20
20 20 mA
AS7C34098 20
20
20 20 mA
5/23/02; v.1.8
Alliance Semiconductor
P. 1 of 12
Copyright © Alliance Semiconductor. All rights reserved.
1 page  
AS7C4098
AS7C34098
®
Read cycle (over the operating range)
–10
Parameter
Symbol Min Max
Read cycle time
tRC 10 –
Address access time
tAA – 10
Chip enable (CE) access time
tACE – 10
Output enable (OE) access time
tOE – 5
Output hold from address change
tOH
3–
CE Low to output in low Z
tCLZ 0 –
CE High to output in higfch Z
tCHZ – 5
OE Low to output in low Z
tOLZ 0 –
OE High to output in high Z
tOHZ – 5
LB, UB access time
tBA – 5
LB, UB Low to output in low Z
tBLZ 0 –
LB, UB High to output in high Z
tBHZ – 5
Power up time
tPU 0 –
Power down time
tPD – 10
–12
Min Max
12 –
– 12
– 12
–6
3–
3–
–6
0–
–6
–6
0–
–6
0–
– 12
–15
Min Max
15 –
– 15
– 15
–7
3–
0–
–7
0–
–7
–7
0–
–7
0–
– 15
–20
Min Max
20 –
– 20
– 20
–8
3–
0–
–9
0–
–9
–8
0–
–9
0–
– 20
Unit Notes
ns
ns
ns
ns
ns 5
ns 4, 5
ns 4, 5
ns 4, 5
ns 4, 5
ns
ns
ns
ns 5
ns 5
Key to switching waveforms
Rising input
Falling input
Read waveform 1 (address controlled)
Address
DataOUT
tOH
Previous data valid
tAA
tRC
Data valid
Undefined/don’t care
tOH
5/23/02; v.1.8
Alliance Semiconductor
P. 5 of 12
5 Page 
Bottom View
6 543 2
1
A
B
C
D
E
F
G
H
A
B1
®
48-ball FBGA
Ball #A1
C1
A
AS7C4098
AS7C34098
Top View
Ball #A1 index
SRAM Die
C
Elastomer
B
Side View
E2
E
D
Die
E1
Minimum Typical Maximum
A – 0.75 –
B 6.90 7.00 7.10
B1 – 3.75 –
C 10.90 11.00 11.10
C1 – 5.25 –
D 0.30 0.35 0.40
E–
– 1.20
E1 – 0.68 –
E2 0.22 0.25 0.27
Y–
– 0.08
Detail View
A
E2
E
Die
Y
0.3/Typ
Notes
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
4. All tolerance are ±0.050 unless otherwise specified.
5. Typ: typical.
6. Y is coplanarity: 0.08 (max).
5/23/02; v.1.8
Alliance Semiconductor
P. 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AS7C4098-12JI.PDF ] | |
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