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AS7C34098-12TI fiches techniques PDF

Alliance Semiconductor - 5V/3.3V 256K x 16 CMOS SRAM

Numéro de référence AS7C34098-12TI
Description 5V/3.3V 256K x 16 CMOS SRAM
Fabricant Alliance Semiconductor 
Logo Alliance Semiconductor 





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AS7C34098-12TI fiche technique
March 2002
®
5V/3.3V 256K × 16 CMOS SRAM
AS7C4098
AS7C34098
Features
• AS7C4098 (5V version)
• AS7C34098 (3.3V version)
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/max @ 12 ns
- 468 mW (AS7C34098)/max @ 12 ns
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
I/O
buffer
1024 × 256 × 16
Array
(4,194,304)
Control circuit
Column decoder
VCC
GND
UB
OE
LB
CE
• Low power consumption: STANDBY
- 110 mW (AS7C4098)/max CMOS
- 72 mW (AS7C34098)/max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
- 48-ball FBGA 7 x 11 mm
• ESD protection 2000 volts
• Latch-up current 200 mA
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
IV/COC12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
–10 –12 –15 –20 Unit
10 12 15 20 ns
56
7 9 ns
AS7C4098
250 220 180 mA
AS7C34098 160
130
110
100 mA
AS7C4098
20
20 20 mA
AS7C34098 20
20
20 20 mA
5/23/02; v.1.8
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.

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