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Número de pieza | AS6C1016 | |
Descripción | 64K X 16 BIT LOW POWER CMOS SRAM | |
Fabricantes | Alliance Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AS6C1016 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
No Preview Available ! AS6C1016
64K X 16 BIT LOW POWER CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Description
Initial Issue
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package
available
Added packing type in ORDERING INFORMATION
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Revised PACKAGE OUTLINE DIMENSION in page 11
Revised VDR to 1.5V
Revised ORDERING INFORMATION in page 12
Revised typo in PRODUCT FAMILY page 1
Deleted E Grade
Issue Date
Nov.19.2008
May.6.2010
Aug.30.2010
Oct.4.2010
Aug.9.2011
Alliance Memory, Inc.
Rev. 1.4
0
1 page AS6C1016
64K X 16 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN -
Input/Output Capacitance
CI/O -
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
MAX
6
8
UNIT
pF
pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
LB#, UB# to High-Z Output
LB#, UB# to Low-Z Output
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
tBA
tBHZ*
tBLZ*
AS6C1016-55
MIN.
MAX.
55 -
- 55
- 55
- 30
10 -
5-
- 20
- 20
10 -
- 55
- 25
10 -
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYM.
AS6C1016-55
MIN.
MAX.
Write Cycle Time
tWC 55
-
Address Valid to End of Write
tAW
50
-
Chip Enable to End of Write
tCW 50
-
Address Set-up Time
tAS 0 -
Write Pulse Width
tWP 45
-
Write Recovery Time
tWR 0
-
Data to Write Time Overlap
tDW 25
-
Data Hold from End of Write Time tDH 0 -
Output Active from End of Write
tOW*
5
-
Write to Output in High-Z
tWHZ*
-
20
LB#, UB# Valid to End of Write
tBW
50
-
*These parameters are guaranteed by device characterization, but not production tested.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alliance Memory, Inc.
Rev. 1.4
4
5 Page AS6C1016
64K X 16 BIT LOW POWER CMOS SRAM
48-ball 6mm × 8mm TFBGA Package Outline Dimension
Alliance Memory, Inc.
Rev. 1.4
10
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet AS6C1016.PDF ] |
Número de pieza | Descripción | Fabricantes |
AS6C1016 | 64K X 16 BIT LOW POWER CMOS SRAM | Alliance Semiconductor |
AS6C1016-55BIN | 64K X 16 BIT LOW POWER CMOS SRAM | Alliance Semiconductor |
AS6C1016-55ZIN | 64K X 16 BIT LOW POWER CMOS SRAM | Alliance Semiconductor |
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