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PDF AS6C2016-55ZIN Data sheet ( Hoja de datos )
| Número de pieza | AS6C2016-55ZIN | |
| Descripción | 128K X 16 BIT LOW POWER CMOS SRAM | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
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JFaEnBuRaUrAy R2Y0027008
AS6C2016
128K X 16 BIT LO5W1P2OKWXER8CBMIOTSLSORAWMPOWER CMOS SRAM
FEATURES
Fast access time : 55ns
Low power consumption:
Operating current : 20/18mA (TYP.)
Standby current : 2µA (TYP.)
Single 2.7V ~ 5.5V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage : 2.0V (MIN.)
Lead free and green package available
Package : 44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Product
Family
AS6C2016 (I)
Operating
Temperature
-40 ~ 85℃
Vcc Range
2.7 ~ 5.5V
GENERAL DESCRIPTION
The AS6C2016 is a 2,097,152-bit low power
CMOS static random access memory organized as
131,072 words by 16 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The AS6C2016 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The AS6C2016 operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
Speed
55ns
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
2µA 20/18mA
FEBRUARY/2008, V 1.c
Alliance Memory Inc.
Page 1 of 13
1 page  
JFaEnBuRaUrAy R2Y0027008
AS6C2016
128K X 16 BIT LO5W1P2OKWXER8CBMIOTSLSORAWMPOWER CMOS SRAM
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -2mA/4mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
LB#, UB# to High-Z Output
LB#, UB# to Low-Z Output
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
tBA
tBHZ*
tBLZ*
AS6C2016-55
MIN.
MAX.
55 -
- 55
- 55
- 30
10 -
5-
- 20
- 20
10 -
- 55
- 25
10 -
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYM.
AS6C2016-55
MIN.
MAX.
Write Cycle Time
tWC 55
-
Address Valid to End of Write
tAW
50
-
Chip Enable to End of Write tCW 50
-
Address Set-up Time
tAS 0 -
Write Pulse Width
tWP 45
-
Write Recovery Time
tWR 0
-
Data to Write Time Overlap
tDW 25
-
Data Hold from End of Write Time tDH 0 -
Output Active from End of Write
tOW*
5
-
Write to Output in High-Z
tWHZ*
-
20
LB#, UB# Valid to End of Write
tBW
50
-
*These parameters are guaranteed by device characterization, but not production tested.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FEBRUARY/2008, V 1.c
Alliance Memory Inc.
Page 5 of 13
5 Page 
JFaEnBuRaUrAy R2Y0027008
AS6C2016
128K X 16 BIT LO5W1P2OKWXER8CBMIOTSLSORAWMPOWER CMOS SRAM
48-ball 6mm × 8mm TFBGA Package Outline Dimension
FEBRUARY/2008, V 1.c
Alliance Memory Inc.
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AS6C2016-55ZIN.PDF ] | |
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