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PDF AS6C4016-55BIN Data sheet ( Hoja de datos )
| Número de pieza | AS6C4016-55BIN | |
| Descripción | 256K X 16 BIT SUPER LOW POWER CMOS SRAM | |
| Fabricantes | Alliance Semiconductor | |
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JMaAnuRCarHy 20087
AS6C4016
256K X 16 BIT SUPER 5L1O2WKPXO8WBERITCLMOOWS SPROAWMER CMOS SRAM
FEATURES
Fast access time : 55ns
Low power consumption:
Operating current : 30mA (TYP.)
Standby current : 4 A (TYP.) LL-version
Single 2.7V ~ 5.5V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage :1.5V(MIN.)
Lead free and green package available
Package : 44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Product
Family
(I)
Operating
Temperature
-40 ~ 85
Vcc Range
2.7 ~ 5.5V
GENERAL DESCRIPTION
The is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
Speed
55ns
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
4µA(LL)
30mA
FUNCTIONAL BLOCK DIAGRAM
L WW
L AA
O
V
OU OO U
CC
M7 2 c/2
CC
R YY2 c/2
T
O RT
R
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A17
Address Inputs
DQ0 – DQ15 Data Inputs/Outputs
CE# Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
LB# Lower Byte Control
UB# Upper Byte Control
VCC Power Supply
VSS Ground
I TO
O RT
R
MARCH/2008, V 1.0
Alliance Memory Inc.
Page 1 of 12
1 page  
JMaAnuRCarHy 20087
AS6C4016
256K X 16 BIT SUPER 5LO12WKPOXW8EBR ICTMLOOS WSRAPMOWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Address
CE#
LB#,UB#
OE#
Dout
tRC
tAA
tACE
tBA
tOLZ
tBLZ
tCLZ
tOE
High-Z
tOH
tOHZ
tBHZ
tCHZ
Data Valid
High-Z
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
MARCH/2008, V 1.0
Alliance Memory Inc.
Page 5 of 12
5 Page 
JMaAnuRCarHy 20087
AS6C4016
256K X 16 BIT SUPER 5LO12WKPOXW8EBR ICTMLOOS WSRAPMOWER CMOS SRAM
Alliance
AS6C4016-55ZIN
AS6C4016-55BIN
Organization
VCC
Range
Package
Operating Temp
256K x 16
256K x 16
2.7 - 5.5V
2.7 - 5.5V
44pin TSOP II Industrial ~ -40 C - 85 C
48ball TFBGA Industrial ~ -40 C - 85 C
Speed
ns
55
55
Part Numbering System
AS6C
4016
low power
S RAM prefix
Device Number
40 = 4M
16 =x16
-55
Access
Time
X
Package Option
44pin TSOP II
48ball TFBGA
XN
Temperature Range
I = Industrial
(-40 to + 85 C)
N = Lead Free
RoHS
compliant part
MARCH/2008, V 1.0
Alliance Memory Inc.
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AS6C4016-55BIN.PDF ] | |
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