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PDF AS6C8016-55BIN Data sheet ( Hoja de datos )
| Número de pieza | AS6C8016-55BIN | |
| Descripción | 512K X 16 BIT SUPER LOW POWER CMOS SRAM | |
| Fabricantes | Alliance Semiconductor | |
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JNaOnVuEaMryB2E0R027007
AS6C8016
512K X 16 BIT SUPER 5L1O2WKPXO8WBERITCLMOOWS SPROAWMER CMOS SRAM
FEATURES
Fast access time : 55ns
Low power consumption:
Operating current : 30mA (TYP.)
Standby current : 6µA (TYP.) LL-version
Single 2.7V ~ 5.5V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage : 1.5V (MIN.)
Lead free and green package available
Package : 44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Product
Family
AS6C8016(I)
Operating
Temperature
-40 ~ 85℃
Vcc Range
2.7 ~ 5.5V
GENERAL DESCRIPTION
The AS6C8016 is a 8,388,608-bit low power
CMOS static random access memory organized as
524,288 words by 16 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
The AS6C8016 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The AS6C8016 operates from a single power
supply of 2.7V ~ 5.5V and all inputs and outputs are
fully TTL compatible
Speed
55ns
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
6µA(LL)
30mA
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0-A18
DECODER
512Kx16
MEMORY ARRAY
DQ0-DQ7
Lower Byte
DQ8-DQ15
Upper Byte
I/O DATA
CIRCUIT
COLUMN I/O
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A18
Address Inputs
DQ0 – DQ15 Data Inputs/Outputs
CE# Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
LB# Lower Byte Control
UB# Upper Byte Control
VCC Power Supply
VSS Ground
CE#
WE#
OE#
LB#
UB#
CONTROL
CIRCUIT
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 1 of 12
1 page  
JNaOnVuEaMryB2E0R027007
AS6C8016
512K X 16 BIT SUPER 5LO12WKPOXW8EBR ICTMLOOS WSRAPMOWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Address
Dout
tRC
Previous Data Valid
tAA
tOH
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Address
CE#
LB#,UB#
OE#
Dout
tRC
tAA
tACE
tBA
tOLZ
tBLZ
tCLZ
tOE
High-Z
tOH
tOHZ
tBHZ
tCHZ
Data Valid
High-Z
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 5 of 12
5 Page 
JNaOnVuEaMryB2E0R027007
AS6C8016
512K X 16 BIT SUPER 5L1O2WKPOXW8EBRICTMLOOSWSRAPMOWER CMOS SRAM
ORDERING INFORMATION
Alliance
Organization
VCC
Range
AS6C8016 -55ZIN
AS6C8016 -55BIN
512K x 16
512K x 16
2.7 - 5.5V
2.7 - 5.5V
Package
44pin TSOP II
48ball TBGA
Operating Temp
Speed
ns
Industrial ~ -40 C - 85 C
Industrial ~ -40 C - 85 C
55
55
PART NUMBERING SYSTEM
AS6C
low power
SRAM prefix
8016
Device Number
80 = 8M
16 = x16
-55
Access
Time
X XN
Package Option
Z - 44pin TSOP
B = 48ball TFBGA
Temperature Range
I = Industrial
(-40 to + 85 C)
N = Lead Free
RoHS
compliant part
NOVEMBER/2007, V 1.0
Alliance Memory Inc.
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AS6C8016-55BIN.PDF ] | |
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