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PDF AS6C1616A Data sheet ( Hoja de datos )
| Número de pieza | AS6C1616A | |
| Descripción | 1024K X 16 BIT LOW POWER CMOS SRAM | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
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AUGUST 2010
AS6C1616A
1024K X 16 BIT LOW POWER CMOS SRAM
FEATURES
GENERAL DESCRIPTION
• Process Technology : 0.15μm Full CMOS
• Organization : 1M x 16 bit
• Power Supply Voltage : 2.7V ~ 3.6V
• Low Data Retention Voltage : 1.5V(Min.)
• Three state output and TTL Compatible
• Package Type : 48-FPBGA
TheAS6C1616A - 55%,1 is fabricated by Alliance's
advanced full CMOS process technology. The device
supports industrial temperature range and Chip Scale
Package for user flexibility of system design. The device
also supports low data retention voltage for battery back-
up operation with low data retention current.
PRODUCT FAMILY
Product
Family
Operating
Temperature
Vcc
Range
AS6C1616A - 55 BIN
Industrial
(-40 ~ 85oC)
2.7 ~ 3.6 V
Speed
55ns
Power Dissipation
Standby
Operating
(ISB1, Typ.) (ICC1.Max.)
PKG
Type
4 μA1)
8 mA
48-FPBGA
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
DQ0 ~ DQ7
DQ8 ~ DQ15
Memory Array
1M x 16
Data
Cont I/O Circuit
Data
Cont Column Select
VCC
VSS
A11 A12 A13 A14 A15 A16 A17 A18 A19
WE
OE
UB Control Logic
LB
CS1
CS2
1
1 page  
AUGUST 2010
1024K X 16 BIT LOW POWER CMOS SRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.4V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL1) = 100pF+ 1 TTL(70nsec)
CL1) = 30pF + 1 TTL(45ns/55ns)
1. Including scope and Jig capacitance
2. R1=3070Ω, R2=3150Ω
3. VTM=2.8V
4. CL = 5pF + 1 TTL (measurement with tLZ, tHZ, tOLZ, tOHZ, tWHZ)
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
55ns
Min Max
Unit
Read cycle time
tRC 55 -
ns
Address access time
tAA
- 55
ns
Chip select to output
tCO1, tCO2
-
55
ns
Output enable to valid output
tOE
- 35
ns
UB, LB access time
tBA 55 ns
Chip select to low-Z output
tLZ1, tLZ2
5
-
ns
UB, LB enable to low-Z output
tBLZ 5 -
ns
Output enable to low-Z output
tOLZ 5 -
ns
Chip disable to high-Z output
tHZ1, tHZ2
0
20
ns
UB, LB disable to how-Z output
tBHZ
0 20
ns
Output disable to high-Z output
tOHZ
0 20
ns
Output hold from address change
tOH 10 -
ns
CL1)
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
55ns
Min Max
Unit
Write cycle time
tWC 55 -
ns
Chip select to end of write
tCW1, tCW2
45
-
ns
Address setup time
tAS 0 - ns
Address valid to end of write
tAW 45 -
ns
UB, LB valid to end of write
tBW 45 -
ns
Write pulse width
tWP 45 -
ns
Write recovery time
tWR 0 - ns
Write to ouput high-Z
tWHZ
0 20
ns
Data to write time overlap
tDW 25
ns
Data hold from write time
tDH 0 - ns
End write to output low-Z
tOW 5 - ns
AS6C1616A
VTM3)
R12)
R22)
5
5 Page 
AUGUST 2010
1024K X 16 BIT LOW POWER CMOS SRAM
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch)
AS6C1616A
Unit: millimeters
Top View
B
Bottom View
B
B1
A1 index Mark
0.5
6 5 4 3 21
A
#A1 B
C
D
E
F
G
H
Side View
D
C
Min
A-
B 7.95
B1 -
C 9.95
C1 -
D 0.30
E-
E1 -
E2 0.20
Y-
Typ
0.75
8.00
3.75
10.00
5.25
0.35
-
-
0.25
-
Max
-
8.05
-
10.05
-
0.40
1.00
0.70
0.30
0.08
B/2
Detail A
A
Y
NOTES.
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75x0.75) (typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AS6C1616A.PDF ] | |
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