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Número de pieza | AS6nvLC512K8DCG-25XT | |
Descripción | 512K x 8 / 256K x 16 nvSRAM | |
Fabricantes | Micross Components | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AS6nvLC512K8DCG-25XT (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
No Preview Available ! ADVANCE INFORMATION nvSRAM
AS6nvLC512K8
AS6nvLC256K16
512K x 8 / 256K x 16 nvSRAM
3.3V High Speed SRAM with
Non-Volatile Storage
AVAILABLE AS MILITARY
SPECIFICATIONS
• Military Processing (MIL-STD-883C para 1.2.2)
• Temperature Range -55C to 125C
FEATURES
• -55oC to 125oC Operation
• True non-volatile SRAM (no batteries)
• 20 ns, 25 ns, and 45 ns access times
• Automatic STORE on power down with only a small
capacitor
• STORE to QuantumTrap® nonvolatile elements initiated by
software, device pin, or AutoStore® on power down
• RECALL to SRAM initiated by software or power up
• Infinite Read, Write, and Recall cycles
• 200,000 STORE cycles to QuantumTrap
• 20 year data retention
• Single 3.3V +.3V/-3V operation
• Ceramic Hermetic 44 Gullwing
-Can order with X7R CAPS on package
-Matches footprint of plastic 44 TSOP
• MIL-STD-883 Processing
FUNCTIONAL DESCRIPTION
The AS6nvLC512K8 / AS6nvLC256K16 is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is organized as
512K bytes of 8 bits each or 256K words of 16 bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology, producing
the world’s most reliable nonvolatile memory. The SRAM provides
infinite read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers from
the SRAM to the nonvolatile elements (the STORE operation) takes
place automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available under
software control.
LOGIC BLOCK DIAGRAM
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Notes
1. Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
AS6nvLC512K8
AS6nvLC256K16
Rev. 0.2 06/10
1
%+(
Micross Components reserves the right to change products or specifications without notice.
1 page Mode Selection (continued)
ADVANCE INFORMATION nvSRAM
AS6nvLC512K8
AS6nvLC256K16
CE\
WE\
OE\,BHE\,BLE\13
A15ͲA07
Mode
I/O
Power
L
H
L
0x4E38
ReadSRAM
OutputData
Active8
0xB1C7
ReadSRAM
OutputData
0x83E0
ReadSRAM
OutputData
0x7C1F
ReadSRAM
OutputData
0x703F
ReadSRAM
OutputData
0x4B46
AutoStoreEnable OutputData
L
H
L
0x4E38
ReadSRAM
OutputData
ActiveICC28
0xB1C7
ReadSRAM
OutputData
0x83E0
ReadSRAM
OutputData
0x7C1F
ReadSRAM
OutputData
0x703F
ReadSRAM
OutputData
0x8FC0
NonvolatileStore OutputHighZ
L
H
L
0x4E38
ReadSRAM
OutputData
Active8
0xB1C7
ReadSRAM
OutputData
0x83E0
ReadSRAM
OutputData
0x7C1F
ReadSRAM
OutputData
0x703F
ReadSRAM
OutputData
0x4C63
Nonvolatile
OutputHighZ
Recall
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable
sequence. A sequence of read operations is performed in a manner
similar to the software STORE initiation. To initiate the AutoStore
disable sequence, the following sequence of CE controlled read
operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a manner
similar to the software RECALL initiation. To initiate the AutoStore
enable sequence, the following sequence of CE controlled read
operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual STORE
operation (hardware or software) must be issued to save the AutoStore
state through subsequent power down cycles. The part comes from the
factory with AutoStore enabled.
Data Protection
The AS6nvLC512K8 / AS6nvLC256K16 protects data from
corruption during low voltage conditions by inhibiting all externally
initiatedSTORE and write operations. The low voltage condition
is detected when VCC < VSWITCH. If the AS6nvLC512K8 /
AS6nvLC256K16 is in a write mode (both CE and WE are LOW) at
power up, after a RECALL or STORE, the write is inhibited until the
SRAM is enabled after tLZHSB (HSB to output active). This protects
against inadvertent writes during power up or brown out conditions.
AS6nvLC512K8
AS6nvLC256K16
Rev. 0.2 06/10
Micross Components reserves the right to change products or specifications without notice.
5
5 Page Address
CE
BHE, BLE
WE
Data Input
Data Output
Address
CE
BHE, BLE
WE
Data Input
Data Output
ADVANCE INFORMATION nvSRAM
AS6nvLC512K8
AS6nvLC256K16
SRAM Write Cycle #2: CE\ Controlled3, 16, 17, 18
tWC
Address Valid
tSA tSCE
tHA
tBW
tPWE
tSD tHD
Input Data Valid
High Impedance
SRAM Write Cycle #3: BHE\ and BLE\ Controlled3, 16, 17, 18
tWC
Address Valid
tSCE
tSA tBW
tHA
tAW
tPWE
tSD tHD
Input Data Valid
High Impedance
AS6nvLC512K8
AS6nvLC256K16
Rev. 0.2 06/10
11
Micross Components reserves the right to change products or specifications without notice.
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet AS6nvLC512K8DCG-25XT.PDF ] |
Número de pieza | Descripción | Fabricantes |
AS6nvLC512K8DCG-25XT | 512K x 8 / 256K x 16 nvSRAM | Micross Components |
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